F81867
I2C Interface DATA pin. AMD TSI & Intel PCH
(IBX Peak) data pin.
SDA
Ilv/OD16st, 5v
5.8 ACPI, ERP
Pin
Pin Name
Type
PWR
Description
Standby power rail control pin 0. This pin controls an
external PMOS to turn on or off the standby power
rail.
ERP_CTRL0#
GPIO00
OD12,5V
52
I_VSB3V
In the S5 state, the default is set to 1 to cut off the
standby power rail.
I/OOD12st,5v
General purpose IO.
Standby power rail control pin 1. This pin controls an
external PMOS to turn on or off the standby power
rail.
ERP_CTRL1#
OD12,5V
53
54
I_VSB3V
I_VSB3V
In the S5 state, the default is set to 1 to cut off the
standby power rail.
GPIO01
I/OOD12st,5v
General purpose IO.
This pin asserts low when the PCH is planning to
enter the DSW power state. It can detect 5VDUAL
level with delay setting supported. The delay time is
1ms~8S (default 4s)
SUS_WARN#
INst
GPIO02
SUS_ACK#
GPIO03
I/OOD12st,5v
OD12,5v
General purpose IO.
This pin must wait SUSWARN# signal for entering
DSW power state.
55
56
I_VSB3V
I_VSB3V
I/OOD12st,5v
General purpose IO.
This pin asserts low which comes from PCH to shut
off suspend power rails externally to enhance power
saving function.
SLP_SUS#
INst,lv
GPIO04
GPIO05
I/OOD12st,5v
I/OOD12st,5v
General purpose IO.
General purpose IO.
57
58
I_VSB3V
I_VSB3V
UART Serial Output. Used to transmit serial data out to
the communication link.
SOUT5
GPIO06
O12
General purpose IO.
I/OOD12st,5v
UART Serial Input. Used to receive serial data
through the communication link.
General purpose IO.
SIN5
INt,5v
GPIO07
I/OOD12st,5v
UART Request To Send. An active low signal informs
the modem or data set that the controller is ready to
send data.
59
I_VSB3V
RTS5#
O12
GPIO10
LED_VSB
GPIO11
I/OOD12st,5v
OOD12,5V
General purpose IO.
65
66
67
I_VSB3V
I_VSB3V
Power LED for VSB.
I/OOD12st,5v
OOD12,5V
General purpose IO.
Power LED for VCC.
LED_VCC
I2C Interface CLOCK pin. Clock output for AMD TSI
& Intel PCH (IBX Peak).
SCL
Ilv/OD12st, 5v I_VSB3V
24
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
