F81867
7.16 UART3 Registers (CR12)
“-“ Reserved or Tri-State
Register 0x[HEX]
Default Value
Register Name
Device Enable Register
MSB
LSB
30
-
-
0
1
-
-
0
1
-
-
0
0
-
-
0
1
0
-
-
0
0
0
-
-
1
1
0
1
0
0
0
0
0
60
61
F0
F2
F4
F5
F0
F6
Base Address High Register
Base Address Low Register
IRQ Share Register
0
1
-
1
0
1
0
0
0
0
0
Clock Select Register
0
-
0
-
0
-
0
-
9bit-mode Slave Address Register
9bit-mode Slave Address Mask Register
IRQ Share Register
-
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
FIFO Mode Register
UART 3 Device Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
Description
7-1
Reserved
-
-
-
Reserved
0: disable UART 3 I/O Port.
1: enable UART 3 I/O Port.
0
UART3_EN
R/W LRESET#
1
Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0
BASE_ADDR_HI
R/W LRESET#
03h The MSB of UART 3 base address.
Base Address Low Register ⎯ Index 61h
Bit
Name
R/W
Default
Description
Reset
7-0
BASE_ADDR_LO
R/W LRESET# E8h The LSB of UART 3 base address.
IRQ Channel Select Register ⎯ Index 70h
Bit
7-4
3-0
Name
R/W Reset Default
Description
Reserved
-
-
-
Reserved.
Select the IRQ channel for UART 3.
SELUART3IRQ
R/W LRESET#
3h
IRQ Share Register ⎯ Index F0h
Bit
Name
R/W Reset Default
Description
0: normal UART function
1: enable 9-bit mode (multi-drop mode).
7
9BIT_MODE
R/W LRESET#
R/W LRESET#
0
In the 9-bit mode, the parity bit becomes the address/data bit.
This bit works only in 9-bit mode.
0: the SM2 bit will be cleared by host, so that data could be received.
6
AUTO_ADDR
0
1: the SM2 bit will be cleared by hardware according to the sent address and
the given address (or broadcast address derived by SADDR and SADEN)
195
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
