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F81867D 参数 Datasheet PDF下载

F81867D图片预览
型号: F81867D
PDF下载: 下载PDF文件 查看货源
内容描述: 6个UART μSuper IO 128字节FIFO和省电功能 [6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions]
分类和应用: 先进先出芯片
文件页数/大小: 315 页 / 2394 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F81867  
Line Control Register (LCR) Base + 3  
Bit  
Name  
R/W Reset Default  
Description  
0: Divisor Latch can’t be accessed.  
1: Divisor Latch can be accessed via Base and Base+1.  
0: Transmitter is in normal condition.  
1: Transmit a break condition.  
XX0: Parity Bit is disable  
7
DLAB  
R/W LRESET#  
R/W LRESET#  
0
0
6
SETBRK  
5
4
STKPAR  
EPS  
R/W LRESET#  
R/W LRESET#  
0
0
001: Parity Bit is odd.  
011: Parity Bit is even  
101: Parity Bit is logic 1  
111: Parity Bit is logic 0  
3
2
PEN  
STB  
R/W LRESET#  
R/W LRESET#  
0
0
0: Stop bit is one bit  
1: When word length is 5 bit stop bit is 1.5 bit  
else stop bit is 2 bit  
00: Word length is 5 bit  
01: Word length is 6 bit  
10: Word length is 7 bit  
1-0  
WLS  
R/W LRESET#  
00  
11: Word length is 8 bit  
MODEM Control Register (MCR) Base + 4  
Bit  
Name  
R/W Reset Default  
Description  
Reserved.  
7-5  
Reserved  
-
LRESET#  
-
0: UART in normal condition.  
1: UART is internal loop back  
0: All interrupt is disabled.  
1: Interrupt is enabled (disabled) by IER.  
Read from MSR[6] while in loop back mode  
4
LOOP  
R/W LRESET#  
0
3
2
1
OUT2  
OUT1  
RTS  
R/W LRESET#  
R/W LRESET#  
R/W LRESET#  
0
0
0
0: RTS# is forced to logic 1  
1: RTS# is forced to logic 0  
0: DTR# is forced to logic 1  
1: DTR# is forced to logic 0  
0
DTR  
R/W LRESET#  
0
Line Status Register (LSR) Base + 5  
Bit  
Name  
R/W Reset Default  
Description  
0: No error in the FIFO when FIFO is enabled  
1: Error in the FIFO when FIFO is enabled.  
0: Transmitter is in transmitting.  
1: Transmitter is empty.  
7
RCR_ERR  
R
R
R
R
R
R
R
R
LRESET#  
LRESET#  
LRESET#  
LRESET#  
LRESET#  
LRESET#  
LRESET#  
LRESET#  
0
1
1
0
0
0
0
0
6
5
4
3
2
1
0
TEMT  
THRE  
BI  
0: Transmitter Holding Register is not empty.  
1: Transmitter Holding Register is empty.  
0: No break condition detected.  
1: A break condition is detected.  
0: Data received has no frame error.  
1: Data received has frame error.  
0: Data received has no parity error.  
1: Data received has parity error.  
0: No overrun condition occurred.  
1: An overrun condition occurred.  
0: No data is ready for read.  
FE  
PE  
OE  
DR  
1: Data is received.  
112  
Dec, 2011  
V0.12P  
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