F81867
Divisor Latch (MSB) ⎯ Base + 1
Bit
Name
R/W Reset Default
Description
Description
Baud generator divisor high byte.
Access only when LCR [7] is 1.
7-0
DLM
R/W LRESET#
00h
Interrupt Enable Register (IER) ⎯ Base + 1
Bit
Name
R/W Reset Default
7-5
Reserved
-
-
-
Reserved.
This bit is used only in 9-bit mode and always returns “0” when 9-bit mode is
disabled.
4
SM2
R/WC LRESET#
0
0: The receiver could receive data byte.
1: The receiver could only receive address byte and issue an interrupt when
the address is received.
3
2
EDSSI
ELSI
R/W LRESET#
R/W LRESET#
0
0
Enable Modem Status Interrupt. Access only when LCR [7] is 0.
Enable Line Status Error Interrupt. Access only when LCR [7] is 0.
Enable Transmitter Holding Register Empty Interrupt. Access only when LCR
[7] is 0.
1
0
ETBFI
ERBFI
R/W LRESET#
R/W LRESET#
0
0
Enable Received Data Available Interrupt. Access only when LCR [7] is 0.
Interrupt Identification Register (IIR) ⎯ Base + 2
Bit
Name
R/W Reset Default
Description
0: FIFO is disabled
1: FIFO is enabled.
0: FIFO is disabled
1: FIFO is enabled.
7
FIFO_EN
R
LRESET#
0
6
FIFO_EN
Reserved
R
-
LRESET#
LRESET#
0
-
5-4
Reserved.
000: Interrupt is caused by Modem Status
001: Interrupt is caused by Transmitter Holding Register Empty
010: Interrupt is caused by Received Data Available.
110: Interrupt is caused by Character Timeout
3-1
0
IRQ_ID
R
R
LRESET#
LRESET#
00
1
011: Interrupt is caused by Line Status.
1: Interrupt is not pending.
IRQ_PENDN
0: Interrupt is pending.
FIFO Control Register ⎯ Base + 2
Bit
Name
R/W Reset Default
Description
00: Receiver FIFO trigger level is 1.
01: Receiver FIFO trigger level is 4.
10: Receiver FIFO trigger level is 8.
7-6
RCV_TRIG
W
LRESET#
00
11: Receiver FIFO trigger level is 14.
5-3
2
Reserved
CLRTX
-
LRESET#
LRESET#
LRESET#
-
Reserved.
Reset the transmitter FIFO.
R
R
0
0
Reset the receiver FIFO.
1
CLRRX
0: Disable FIFO.
1: Enable FIFO.
0
FIFO_EN
R
LRESET#
0
111
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
