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F81866A 参数 Datasheet PDF下载

F81866A图片预览
型号: F81866A
PDF下载: 下载PDF文件 查看货源
内容描述: 6个UART超级IO 128字节FIFO和电源 [6 UARTs Super IO With 128 Bytes FIFO and Power]
分类和应用: 先进先出芯片
文件页数/大小: 210 页 / 1806 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F81866A  
Power On/Off  
Control  
(AC Resume)  
Power  
Management  
Event  
Intel DSW  
Hand  
Shaking  
EUP/ERP  
Control  
Control Signal  
Wake up  
RSMRST#  
S3#  
S5#  
PWSIN#  
PWSOUT#  
ATXPG_IN  
PS_ON#  
PWOK  
☆★  
☆★  
☆★  
☆★  
☆★  
PME#  
PS/2 KB/MS  
RI1#/RI2#  
GPIO0x/GPIO1x  
SLP_SUS#  
SUS_ACK#  
SUS_WARN#  
ERP_CTRL0#  
ERP_CTRL1#  
◇: Supported  
: Wake up via ERP  
: Wake up via System  
6.8.1Power Control  
6.8.1.1Wake Up Via Sleep State  
When the system is at the normal sleep state (S3, S4, S5) or deep sleep (G3’) state, F81866A could wake  
up via PWSOUT# & PME#. See below for the related registers:  
CR0A  
Index 0xE0, 0xE8  
CR0A  
Index 0xF0~0xF3  
Wake up by PME#  
Index 0x2D  
Normal Sleep State  
EUP/ERP  
CR 0A  
Index 0x30  
CR0A  
Index 0xE0, 0xE8  
CR0A  
Index 0xF4  
Wake up by PWSOUT#  
Index 0x2D  
Normal Sleep State  
EUP/ERP  
: Supported  
6.8.1.2 Wake Up Stage Detection  
F81866A is counted on the chipset SLP_S3#, SLP_S4#/SLP_S5# stage, to decide the wake up stage as  
below:  
ACPI Stage  
SLP_S3#  
SLP_S4# /SLP_S5#  
S0  
S3  
S5  
H
L
L
H
H
L
H: High; L: Low  
95  
Jan, 2012  
V0. 12P  
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