F81866A
6.6.2.8GPIO7x
PIN STATUS
Register
Power
Well
Pin
Power
Well
Register
Reset Signal
Pin
Name
G3 -> S5
S0
S3
S5
103
104
105
106
107
108
109
110
GPIO70
GPIO71
GPIO72
GPIO73
GPIO74
GPIO75
GPIO76
GPIO77
Z
Z
Z
Z
Z
Z
Z
Z
user define
user define
user define
user define
user define
user define
user define
user define
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
LRESET#
LRESET#
LRESET#
LRESET#
LRESET#
LRESET#
LRESET#
LRESET#
3VCC
3VCC
3VCC
3VCC
3VCC
3VCC
3VCC
3VCC
6.6.2.9GPIO8x
PIN STATUS
Register
Power
Well
Pin
Power
Well
Register
Reset Signal
Pin
Name
G3 -> S5
S0
S3
S5
111
112
113
114
115
116
117
118
GPIO80
GPIO81
GPIO82
GPIO83
GPIO84
GPIO85
GPIO86
GPIO88
Z
Z
Z
Z
Z
Z
Z
Z
user define
user define
user define
user define
user define
user define
user define
user define
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
LRESET#
LRESET#
LRESET#
LRESET#
LRESET#
LRESET#
LRESET#
LRESET#
3VCC
3VCC
3VCC
3VCC
3VCC
3VCC
3VCC
3VCC
6.7 Watchdog Timer Function
Watch dog timer is provided for system controlling. If time-out can trigger one signal to high/low level/pulse, the
signal is depend on register setting.
The time unit has two ways from 1sec or 60sec. In pulse mode, there are four pulse widths can be selected
(1ms/25ms/125ms/5sec). Others, please refer the device register description as below.
Watchdog Timer Configuration Register 1⎯ base address + 05h
Bit
Name
R/W Reset Default
Description
Reserved
7
Reserved
R
-
0
0
If watchdog timeout event occurred, this bit will be set to 1. Write a 1 to this
bit will clear it to 0.
6
WDTMOUT_STS
R/W 5VSB
If this bit is set to 1, the counting of watchdog time is enabled.
5
4
3
WD_EN
WD_PULSE
WD_UNIT
R/W 5VSB
R/W 5VSB
R/W 5VSB
0
0
0
Select output mode (0: level, 1: pulse) of RSTOUT# by setting this bit.
Select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit.
Select output polarity of RSTOUT# (1: high active, 0: low active) by setting
this bit.
2
WD_HACTIVE
R/W 5VSB
0
Select output pulse width of RSTOUT#
1-0
WD_PSWIDTH
R/W 5VSB
0
0: 1 ms
2: 125 ms
1: 25 ms
3: 5 sec
93
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
