F81866A
In order to achieve the lower power consumption, F81866A provides the ERP_CTRL1# to turn off the
V3A so that the system can enter the Fintek G3’ state.
The block diagram below shows how the connection and control method for F81866A and PCH.
ATX Power
5VSB
VCC
V5A
SUS_WARN
MB Logic
5VDUAL
ERP_CTRL0#
3.3V VSB VR
5VDUAL
(SLP_SUS_FET)
(Invert From PCH)
ERP_CTRL1#
5VSB
S0 State
5VDUAL
S3 State
S4/S5
DSW
3VSB
V3A
1.05V
SUS_WARN#
SUS_ACK#
SLP_SUS#
ERP_CTRL0#
ERP_CTRL1#
V3A
SUSWARN#
SUSACK#
SUS_WARN#
V Detect & Delay
G3’
G3
F81866A
CPT PCH
5VA_PWOK#
RSMRST#
DPWROK
RSMRST#
V5A
3VSB
I_3VSB
Fig 6-17
The register for setting this mode is at CR0A, index 0xEC [7:6]. When choose Intel DSW mode,
ERP_CTRL0#, & ERP_CTRL1# would follow SLP_SUS#. When choose Intel DSW + Fintek G3’ mode,
ERP_CTRL0# would follows SLP_SUS#, & ERP_CTRL1# will enter Fintek ERP mode after entering DSW
mode for 6.4s (default, the time is programmable).
In sum, there are three blocks in this mode (Please refer to the application circuit for the HW schematic):
a. DSW Control Block:
a-1 SLP_SUS#: SIO input pin from CPT PCH SLP_SUS#.
a-2 SUS_WARN#: SIO input pin from CPT PCH SUS_WARN#.
a-3 SUS_ACK#: SIO output pin to CPT PCH SUSACK#.
a-4 DPWROK: SIO output pin to CPT PCH DPWROK.
b. ERP Control Block:
b-1 ERP_CTRL0#: Support “CPT PCH DSW” control mode which is a low active signal to turn on/off
3VSB/5VSB power source by P MOSFET.
b-2 ERP_CTRL1#: Support “Fintek G3’ ” control mode which is a low active signal to turn on/off
3VA/5VA power source by P MOSFET.
98
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
