F81866A
6.8.3Power Saving Controller (Fintek ERP Mode)
The two pins, ERP_CTRL0# and ERP_CTRL1#, which control the standby power rail on/off to fulfill the
purpose which decreases the power consumption when the system is in the sleep state or the soft-off state.
These two pins connected to the external PMOSs and the defaults are high in the sleep state in order to cut
off all the standby power rails to save the power consumption. If the system needs to support wake-up
function, the two pins can be programmable to set which power rail to turn on. The programmable register is
powered by the battery. So, the setting is kept even the AC power is lost when the register is set. At the power
saving state (FINTEK calls it G3’ state), the F81866A consumes 5VSB power rail only to realize a low power
consumption system.
The register for setting this mode is at CR0A, index 0xEC [7:6]. When choose Fintek G3’ mode,
ERP_CTRL0# & ERP_CTRL1# will enter S5. After entering S5 for 6.4s (default, the time is programmable),
these two pins would send high level signal and then cut off all the power sources except ATX_5VSB (power
consumption is about 15mW). In order to avoid the inrush current from ATX_5VSB, F81866A also provide the
soft start circuits at these two pins. See the related register for the soft start circuit (CR0A, index 0xEC [4]).
In sum, there are two blocks in this mode (Please refer to the application circuit for the HW schematic):
a. EUP Control Block:
ERP_CTRL0# and ERP_CTRL1# are low active signals to turn on/off 5VSB power source by P MOSFET.
b. Wake Up Event Block via:
Power Button
V
External LAN
V
PCH Internal LAN
X
PS2 KB/Mouse
V
SIO RI#
V
RTC
X
GPIO0x/1x
V
Note:
By pressing/triggering any of the above pin, the system could wake up from the sleep (S4/S5) DSW and G3’ mode.
V: Supported.
X: Does not supported.
99
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
