F81866A
Case Open, Alert, OVT Mode Register ⎯ Index 02h
Bit
Name
R/W Reset Default
Description
Dummy register.
7
Reserved
R/W
-
0
0: Disable case open event output via BEEP.
6
CASE_BEEP_EN
OVT_MODE
R/W
5VSB
0
1: Enable case open event output via BEEP.
00: The OVT# will be low active level mode.
01: The OVT# will be low pulse mode.
5-4
R/W 5VSB
0
10: The OVT# will indicate by 1Hz LED function.
11: The OVT# will indicate by (400/800HZ) BEEP output.
Dummy register.
3
2
Reserved
R/W
-
0
0
0: Disable case open event output via PME.
1: Enable case open event output via PME.
CASE_SMI_EN
R/W 5VSB
00: The ALERT# will be low active level mode.
01: The ALERT# will be high active level mode.
10: The ALERT# will indicate by 1Hz LED function.
11: The ALERT# will indicate by (400/800HZ) BEEP output.
1-0
ALERT_MODE
R/W 5VSB
0
Case Open Status Register ⎯ Index 03h
Bit
Name
R/W Reset Default
Description
Reserved
7-1
Reserved
R/W
-
0
0
Case open event status write 1 to clear if case open event cleared. (This
bit is powered by VBAT.)
0
CASE_STS
R/W VBAT
6.4.2.2PECI/TSI/I2C Setting
TSI Or IBEX Control Register ⎯ Index 08h
Bit
7-1
0
Name
TSI_ADDR
Reserved
R/W Reset Default
Description
AMD TSI or Intel IBEX slave address.
Reserved
R/W
-
5VSB
-
26h
-
I2C Address Control Register ⎯ Index 09h
Bit
7-1
0
Name
I2C _ADDR
Reserved
R/W Reset Default
Description
I2C__ADDR[7:1] is the slave address sent by the embedded master
when using a block write command
R/W
R/W
0
0
5VSB
-
Reserved
46
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
