F81866A
7.7.4.9GPIO0 SMI Enable Register ⎯ Index F8h
Bit
Name
R/W Reset Default
Description
0: Disable SMI event.
7
GPIO07_SMI_EN
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
0
0
0
0
0
0
0
0
1: Enable SMI event via PME# or SIRQ if GPIO07_SMI_ST is set.
0: Disable SMI event.
6
5
4
3
2
1
0
GPIO06_SMI_EN
GPIO05_SMI_EN
GPIO04_SMI_EN
GPIO03_SMI_EN
GPIO02_SMI_EN
GPIO01_SMI_EN
GPIO00_SMI_EN
1: Enable SMI event via PME# or SIRQ if GPIO06_SMI_ST is set.
0: Disable SMI event.
1: Enable SMI event via PME# or SIRQ if GPIO05_SMI_ST is set.
0: Disable SMI event.
1: Enable SMI event via PME# or SIRQ if GPIO04_SMI_ST is set.
0: Disable SMI event.
1: Enable SMI event via PME# or SIRQ if GPIO03_SMI_ST is set.
0: Disable SMI event.
1: Enable SMI event via PME# or SIRQ if GPIO02_SMI_ST is set.
0: Disable SMI event.
1: Enable SMI event via PME# or SIRQ if GPIO01_SMI_ST is set.
0: Disable SMI event.
1: Enable SMI event via PME# or SIRQ if GPIO00_SMI_ST is set.
7.7.4.10GPIO0 SMI Status Register ⎯ Index F9h
Bit
Name
R/W Reset Default
Description
0: No SMI event.
7
GPIO07_SMI_ST
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
0
0
0
0
0
0
0
0
1: A SMI event will set if GPIO07 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
6
5
4
3
2
1
0
GPIO06_SMI_ST
GPIO05_SMI_ST
GPIO04_SMI_ST
GPIO03_SMI_ST
GPIO02_SMI_ST
GPIO01_SMI_ST
GPIO00_SMI_ST
1: A SMI event will set if GPIO06 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1: A SMI event will set if GPIO05 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1: A SMI event will set if GPIO04 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1: A SMI event will set if GPIO03 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1: A SMI event will set if GPIO02 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1: A SMI event will set if GPIO01 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1: A SMI event will set if GPIO00 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
147
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
