F81866A
GPIO06 supports pulse mode.
When pulse mode is selected, write “1” to this bit will assert a pulse from
GPIO06. Auto clear when pulse is finished.
6
5
4
GPIO06_VAL
GPIO05_VAL
GPIO04_VAL
R/W 5VSB
R/W 5VSB
R/W 5VSB
0
0
0
When level mode is selected, write 0/1 to this bit will set the level of GPIO06.
0: outputs 0 when in output mode.
1: outputs 1 when in output mode. GPIO06 will be tri-state if GPIO06_DRV is
clear to “0”.
GPIO05 supports pulse mode.
When pulse mode is selected, write “1” to this bit will assert a pulse from
GPIO05. Auto clear when pulse is finished.
When level mode is selected, write 0/1 to this bit will set the level of GPIO05.
0: outputs 0 when in output mode.
1: outputs 1 when in output mode. GPIO05 will be tri-state if GPIO05_DRV is
clear to “0”.
GPIO04 supports pulse mode.
When pulse mode is selected, write “1” to this bit will assert a pulse from
GPIO04. Auto clear when pulse is finished.
When level mode is selected, write 0/1 to this bit will set the level of GPIO04.
0: outputs 0 when in output mode.
1: outputs 1 when in output mode. GPIO04 will be tri-state if GPIO04_DRV is
clear to “0”.1: GPIO04 outputs 1 when in output mode.
0: GPIO03 outputs 0 when in output mode.
1: GPIO03 outputs 1 when in output mode.
3
2
1
0
GPIO03_VAL
GPIO02_VAL
GPIO01_VAL
GPIO00_VAL
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
1
1
1
1
0: GPIO02 outputs 0 when in output mode.
1: GPIO02 outputs 1 when in output mode.
0: GPIO01 outputs 0 when in output mode.
1: GPIO01 outputs 1 when in output mode.
0: GPIO00 outputs 0 when in output mode.
1: GPIO00 outputs 1 when in output mode.
7.7.4.3GPIO0 Pin Status Register ⎯ Index F2h (This byte could be also read by base address + 6)
Bit
7
Name
R/W Reset Default
Description
The pin status of GPIO07/RTS5#.
GPIO07_IN
GPIO06_IN
GPIO05_IN
GPIO04_IN
GPIO03_IN
GPIO02_IN
GPIO01_IN
GPIO00_IN
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
6
The pin status of GPIO06/SIN5.
5
The pin status of GPIO05/SOUT5.
4
The pin status of SLP_SUS#/GPIO04.
The pin status of SUS_ACK#/GPIO03.
The pin status of SUS_WARN#/GPIO02.
The pin status of ERP_CTRL1#/GPIO01.
The pin status of ERP_CTRL0#/GPIO00.
3
2
1
0
143
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
