F81866A
7.7.4.4GPIO0 Drive Enable Register ⎯ Index F3h
Bit
Name
R/W Reset Default
Description
GPIO07 Drive Enable.
0: GPIO07 is open drain.
1: GPIO07 is push pull.
7
GPIO07_DRV_EN R/W 5VSB
GPIO06_DRV_EN R/W 5VSB
0
0
0
0
0
0
0
0
GPIO06 Drive Enable.
0: GPIO06 is open drain.
1: GPIO06 is push pull.
6
5
4
3
2
1
0
GPIO05 Drive Enable.
0: GPIO05 is open drain.
1: GPIO05 is push pull.
GPIO05_DRV_EN
R/w 5VSB
GPIO04 Drive Enable.
0: GPIO04 is open drain.
1: GPIO04 is push pull.
GPIO04_DRV_EN R/W 5VSB
GPIO03_DRV_EN R/W 5VSB
GPIO02_DRV_EN R/W 5VSB
GPIO01_DRV_EN R/W 5VSB
GPIO00_DRV_EN R/W 5VSB
GPIO03 Drive Enable.
0: GPIO03 is open drain.
1: GPIO03 is push pull.
GPIO02 Drive Enable.
0: GPIO02 is open drain.
1: GPIO02 is push pull.
GPIO01 Drive Enable.
0: GPIO01 is open drain.
1: GPIO01 is push pull.
GPIO00 Drive Enable.
0: GPIO00 is open drain.
1: GPIO00 is push pull.
7.7.4.5GPIO0 Output Mode 1 Register ⎯ Index F4h
Bit
Name
R/W Reset Default
Description
GPIO03 output mode select:
00: Level mode.
01: Inverted level mode.
10: High pulse mode.
11: Low pulse mode.
7-6
GPIO03_MODE
R/W 5VSB
00b
00b
The pulse width is determined by GPIO03_PW_SEL.
GPIO02 output mode select:
00: Level mode.
01: Inverted level mode.
5-4
GPIO02_MODE
R/w 5VSB
10: High pulse mode.
11: Low pulse mode.
The pulse width is determined by GPIO02_PW_SEL.
144
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
