F81866A
F2
F3
F4
F5
F6
F7
F8
F9
GPIO0 Pin Status Register
-
-
-
-
-
-
-
-
GPIO0 Drive Enable Register
GPIO0 Output Mode 1 Register
GPIO0 Output Mode 2 Register
GPIO0 Pulse Width Select 1 Register
GPIO0 Pulse Width Select 2 Register
GPIO0 SMI Enable Register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIO0 SMI Status Register
7.7.4.1GPIO0 Output Enable Register ⎯ Index F0h
Bit
Name
R/W Reset Default
Description
0: GPIO07 is input.
7
GPIO07_OE
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
0
0
0
0
0
0
0
0
1: GPIO07 is output.
0: GPIO06 is input.
1: GPIO06 is output.
6
5
4
3
2
1
0
GPIO06_OE
GPIO05_OE
GPIO04_OE
GPIO03_OE
GPIO02_OE
GPIO01_OE
GPIO00_OE
0: GPIO05 is input.
1: GPIO05 is output.
0: GPIO04 is input.
1: GPIO04 is output.
0: GPIO03 is input.
1: GPIO03 is output.
0: GPIO02 is input.
1: GPIO02 is output.
0: GPIO01 is input.
1: GPIO01 is output.
0: GPIO00 is input.
1: GPIO00 is output.
7.7.4.2GPIO0 Output Data Register ⎯ Index F1h (This byte could be also written by base address + 6)
Bit
Name
R/W Reset Default
Description
GPIO07 supports pulse mode.
When pulse mode is selected, write “1” to this bit will assert a pulse from
GPIO07. Auto clear when pulse is finished.
7
GPIO07_VAL
R/W 5VSB
0
When level mode is selected, write 0/1 to this bit will set the level of GPIO07.
0: outputs 0 when in output mode.
1: outputs 1 when in output mode. GPIO07 will be tri-state if GPIO07_DRV is
clear to “0”.
142
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
