F81218
6.3.5 UART 2 Clock Select Register – index F0h
Power-on default [7:0] = 0x00h.
Bit
7:5
Name
Reserved
R/W
R/W
R/W
Description
Return 0 when read.
4
RS485
0: The RTS# is controlled by programming MCR[1]. (offset +4)
1: The RTS# is drive high when transmitting data and sink low when
receiving data.
3
RXW4C_IRB
TXW4C_IRB
R/W
R/W
R/W
0 : No reception delay when SIR is changed from TX to RX.
1 : Reception delay 4 character-time when SIR is changed from TX
to RX.
2
0 : No transmission delay when SIR is changed from RX to TX.
1 : Transmission delay 4 character-time when SIR is changed from
RX to TX.
1:0
SELURACLK1
SELURACLK0
00 : UART 2 clock source is 1.8462MHz ( 24MHz/13 )
01/10/11 selection reserved.
6.3.6 IR 2 Control Register – index F1h
Power-on default [7:0] = 0x44h.
Bit
7:5
Name
Reserved
R/W
R/W
R/W
Description
Return 010b when read.
0X: Disable IR2 function.
4:3
IRB_MODE1
IRB_MODE0
10 : Enable IR2 function, active pulse is 1.6uS.
11 : Enable IR2 function, active pulse is 3/16 bit time.
0 : Full Duplex function for IR self test.
1 : Half Duplex function.
2
Half_Full_Duplex R/W
Return 1 when read.
1
0
TXINV_IRB
RXINV_IRB
R/W
R/W
0 : IRTX2 is not inversed.
1 : Inverse the IRTX2.
0 : IRRX2 is not inversed.
1 : Inverse the IRRX2.
-30-
August, 2007
V0.33P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
