F81218
6.4 UART 3 Device Control Register (LDN 2)
6.4.1 Device Enable Register – index 30h
Power-on default [7:0] = 0x01h when SOUT3/PS_3E8_IRQC is pull-up, else 0x00h.
Bit
7:1
Name
Reserved
URC_EN
R/W
R/W
R/W
Description
Return 0 when read.
0 : Disable UART 3.
1 : Enable UART 3.
0
6.4.2 I/O Port Select Register – index 60h
Power-on default [7:0] = 0x03h when SOUT3/PS_3E8_IRQC is pull-up, else 0x00h.
Bit Name R/W Description
7:0 URC_BASE[15:8] R/W UART 3 I/O Port Address high byte.
6.4.3 I/O Port Select Register – index 61h
Power-on default [7:0] = E8h when SOUT3/PS_3E8_IRQC is pull-up, else 0x00h.
Bit
7:0
Name
R/W
Description
UART 3 I/O Port Address low byte.
URC_BASE[7:0]
R/W
6.4.4 IRQ Channel Select Register – index 70h
Power-on default [7:0] = 0x05h when SOUT3/PS_3E8_IRQC is pull-up, else 0x00h.
Bit
7:6
Name
Reserved
R/W
R/W
R/W
Description
Return 0 when read.
5
URCIRQ_MODE
0 : PCI IRQ sharing mode.
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
0 : IRQ is not sharing with other device.
4
URCIRQ_SHAR
R/W
-31-
August, 2007
V0.33P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
