F81218
6.2 UART 1 Device Control Register (LDN 0)
6.2.1 Device Enable Register – index 30h
Power-on default [7:0] = 0x01h when SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA is pull-up,
else 0x00h.
Bit
7:1
Name
Reserved
URA_EN
R/W
R/W
R/W
Description
Return 0 when read.
0 : Disable UART 1.
1 : Enable UART 1..
0
6.2.2 I/O Port Select Register – index 60h
Power-on default [7:0] = 0x03h when SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA is pullup,
else 0x00h.
Bit
7:0
Name
R/W
Description
UART 1 I/O Port Address high byte.
URA_BASE[15:8] R/W
6.2.3 I/O Port Select Register – index 61h
Power-on default [7:0] = 0xF8h when SOUT1/PS_3F8_IRQA is pull-up,
0xE0h when DTR1#/PS_3E0_IRQA is pull-up, else 0x00h.
Bit
7:0
Name
R/W
Description
UART 1 I/O Port Address low byte.
URA_BASE[7:0]
R/W
6.2.4 IRQ Channel Select Register – index 70h
Power-on default [7:0] = 0x03h when SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA is pull-up,
else 0x00h
Bit
7:6
Name
Reserved
R/W
R/W
R/W
Description
Return 0 when read.
5
URAIRQ_MODE
0 : PCI IRQ sharing mode.
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
0 : IRQ is not sharing with other device.
1 : IRQ is sharing with other device.
4
URAIRQ_SHAR
R/W
-26-
August, 2007
V0.33P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
