U2
U3
20
1
20
1
VCC5V
RTS1#
DTR1#
SOUT1
RI1#
CTS1#
DSR1#
SIN1
+12V
RTS1
DTR1
SOUT1-
RI1
CTS1
DSR1
SIN1-
DCD1
VCC5V
RTS3#
DTR3#
SOUT3
RI3#
CTS3#
DSR3#
SIN3
+12V
RTS3
DTR3
SOUT3-
RI3
CTS3
DSR3
SIN3-
DCD3
VCC
+12V
VCC
+12V
16
15
13
19
18
17
14
12
5
6
8
2
3
4
7
9
16
15
13
19
18
17
14
12
5
6
8
2
3
4
7
9
P1
P2
DA1
DA2
DA3
RY1
RY2
RY3
RY4
RY5
DY1
DY2
DY3
RA1
RA2
RA3
RA4
RA9
DA1
DA2
DA3
RY1
RY2
RY3
RY4
RY5
DY1
DY2
DY3
RA1
RA2
RA3
RA4
RA9
5
9
4
8
3
7
2
6
1
5
9
4
8
3
7
2
6
1
RI1
RI3
C3
0.1U
DTR1
CTS1
SOUT1-
RTS1
SIN1-
DSR1
DCD1
DTR3
CTS3
SOUT3-
RTS3
SIN3-
DSR3
DCD3
C4
0.1U
DCD1#
DCD3#
11
10
11
10
-12V
-12V
GND
-12V
GND
-12V
DB9
DB9
RS232
(SOP20)
RS232
(SOP20)
(UART1)
(UART3)
U4
U5
20
1
20
1
VCC5V
+12V
VCC5V
+12V
VCC
+12V
VCC
+12V
RTS2
DTR2
SOUT2-
RI2
CTS2
DSR2
SIN2-
DCD2
RTS4
DTR4
SOUT4-
RI4
CTS4
DSR4
SIN4-
DCD4
16
15
13
19
18
17
14
12
5
6
8
2
3
4
7
9
16
15
13
19
18
17
14
12
5
6
8
2
3
4
7
9
P3
P4
RTS2#
DTR2#
SOUT2
RI2#
CTS2#
DSR2#
SIN2
RTS4#
DTR4#
SOUT4
RI4#
DA1
DA2
DA3
RY1
RY2
RY3
RY4
RY5
DY1
DY2
DY3
RA1
RA2
RA3
RA4
RA9
DA1
DA2
DA3
RY1
RY2
RY3
RY4
RY5
DY1
DY2
DY3
RA1
RA2
RA3
RA4
RA9
5
9
4
8
3
7
2
6
1
5
9
4
8
3
7
2
6
1
RI2
RI4
DTR2
CTS2
SOUT2-
RTS2
SIN2-
DSR2
DCD2
DTR4
CTS4
SOUT4-
RTS4
SIN4-
DSR4
DCD4
C5
0.1U
C6
CTS4#
DSR4#
SIN4
0.1U
DCD2#
DCD4#
11
10
11
10
-12V
-12V
GND
-12V
GND
-12V
DB9
DB9
RS232
(SOP20)
RS232
(SOP20)
(UART2)
(UART4)
VCC3V
JP1
1
2
3
4
5
IRRX
IRTX
C7
0.1U
HEADER 5
(IrDA)
Title
Feature Integration Technology Inc.
Size
B
Document Number
UART
Rev
0.2
Date:
Tuesday, January 10, 2006
Sheet
2
of
2
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
