6.5.3 Reset Out (RSTOUT) Function
Please refer to control registers.
6..4 Watchdog Function
Please refer to control register.
7. Registers Description
7.1 Configuration and Control Register – Index 01h
Power-on default [7:0] =0000_1000b
Bit
Name
R/W
PWR
Description
7
INIT
R/W
VSB3V Software reset for all registers including Test Mode registers. Users use
only.
6
CPU_SEL
R/W
VSB3V CPU select, if set this bit to 1 will select AMD CPU, else if set to 0 is Intel
CPU(default), this bit clear by SLOTOCC#, and protect write command
by VID_KEY REG 0x30.
5
4
EN_RSTOUT
EN_OTF
R/W
R/W
VSB3V Enable Reset Out. If set to 1, enable RSTOUT output. Default is disable.
VSB3V If set this bit to 1 will enable VID on the fly mode, user can change new
VID value by program the REG 0x30 VID_OFFSET, this bit will clear by
SLOTOCC#, and protect write command by VID_KEY REG 0x30.
VSB3V Set this bit to 1 to enable Intel VRM10 mode, then GPIO14 and GPIO15
will be implement to VID_IN[5] and VID_OUT[5], this bit default is
enable, , this bit will clear by SLOTOCC#, and protect write command by
VID_KEY REG 0x30.
3
VID_EXTEND
R/W
2
1
Reserved
R/W
VSB3V
AUTO_POWR_ R/W
MODE
VSB3V Set this bit to 1 will enable auto power down mode, when all function are
idle then 20ms the chip will auto power down, it will wakeup when GPIO
state change or read write register
0
SOFT_POWR_ R/W
DOWN
VSB3V Set this bit to 1 will power down all of the analog block and stop internal
clock, write 0 to clear this bit or when GPIO state change will auto clear
this bit to 0.
- 10 -
July, 2007
V0.24P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
