Providing CPU on board detection (SLOTOCC#). The detection circuit is powered by battery. That is latch circuit
is powered by VBAT. The de-bounce circuit should be added to avoid low power noise. The de-bounce circuit is
generated by internal low frequency clock with 32K Hz to filter out the low-to-high or high-to-low glitch.
6.2 Access Interface
The F75121 provides one serial access interface, Serial Bus, to read/write internal registers. The address of Serial
Bus is configurable by using power-on trapping of standby power VBS3V. The pin 11 (GPIO11/I2C _ADDR) is
multi-function pin. During the VSB 3V power-on, this pin serves as input detection of logic high or logic low. This pin is
default pull-down resistor with 100K ohms mapping the Serial Bus address 0x9C (1001_1100). Another Serial Bus
address 0x6E (0110_1110) is set when external pull-up resistor with 10K ohms is connected in this pin.
6.3 The SMBus access timing are shown as follow:
(a) SMBus write to internal address register followed by the data byte
0
7
8
0
7
8
SCL
SDA
0
1
0
1
1
0
1
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Start By
Master
Ack
by
101R
Ack
by
121R
Frame 1
Serial Bus Address Byte
Frame 2
Internal Index Register Byte
0
7
8
SCL (Continued)
SDA (Continued)
D7
D6
D5
D4
D3
D2
D1
D0
Ack
by
784R
Stop
by
Master
Frame 3
Data Byte
Figure 1. Serial Bus Write to Internal Address Register followed by the Data Byte
- 8 -
July, 2007
V0.24P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
