F75111
7.17 GPIO1x Pulse Inverse Register – Index 17h
Power-on default [7:0] =0000_0000b
Bit
Name
R/W
PWR
Description
7
GP17_PULSINV
R/W
VSB3V GPIO 17 Pulse inversed. If the pulse inverse is selected, the output
pulse is high pulse. Default low pulse. The pulse width is defined in
CR14.
6
5
4
3
2
1
0
GP16_PULSINV
GP15_PULSINV
GP14_PULSINV
GP13_PULSINV
GP12_PULSINV
GP11_PULSINV
GP10_PULSINV
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VSB3V GPIO 16 Pulse inversed. If the pulse inverse is selected, the output
pulse is high pulse. Default low pulse. The pulse width is defined in
CR14.
VSB3V GPIO15 Pulse inversed. If the pulse inverse is selected, the output
pulse is high pulse. Default low pulse. The pulse width is defined in
CR14.
VSB3V GPIO14 Pulse inversed. If the pulse inverse is selected, the output
pulse is high pulse. Default low pulse. The pulse width is defined in
CR14.
VSB3V GPIO13 Pulse inversed. If the pulse inverse is selected, the output
pulse is high pulse. Default low pulse. The pulse width is defined in
CR14.
VSB3V GPIO12 Pulse inversed. If the pulse inverse is selected, the output
pulse is high pulse. Default low pulse. The pulse width is defined in
CR14. If this pin services as IRQ/SMI#, this bit has no effect.
VSB3V GPIO 11 Pulse inversed. If the pulse inverse is selected, the output
pulse is high pulse. Default low pulse. The pulse width is defined in
CR14.
VSB3V GPIO10 Pulse inversed. If the pulse inverse is selected, the output
pulse is high pulse. Default low pulse. The pulse width is defined in
CR14.
7.18 GP1X Edge Detector Enable Register – Index 0x18
Power-on default [7:0] =0000_0000b
Bit
Name
R/W
PWR
Description
7
EN_GP17EDGE
R/W
VSB3V Enable GPIO17 Edge Detector. If this bit set to 1 and GPIO17 set to
- 19 -
July, 2007
V0.27P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
