F75111
6
5
4
3
2
1
0
GP16_PSTS
GP15_PSTS
GP14_PSTS
GP13_PSTS
GP12_PSTS
GP11_PSTS
GP10_PSTS
RO
RO
RO
RO
RO
RO
RO
VSB3V Read the GPIO16 data on the pin.
VSB3V Read the GPIO15 data on the pin.
VSB3V Read the GPIO14 data on the pin.
VSB3V Read the GPIO13 data on the pin.
VSB3V Read the GPIO12 data on the pin.
VSB3V Read the GPIO11 data on the pin.
VSB3V Read the GPIO10 data on the pin.
7.13 GPIO1x Level/Pulse Control Register – Index 13h
Power-on default [7:0] =0000_0000b
Bit
Name
R/W
PWR
Description
7
GP17_OMODE R/W
GP16_OMODE R/W
GP15_OMODE R/W
GP14_OMODE R/W
GP13_OMODE R/W
GP12_OMODE R/W
VSB3V GPIO 17 output mode. 0 – level, 1 – pulse.
VSB3V GPIO 16 output mode. 0 – level, 1 – pulse.
VSB3V GPIO 15 output mode. 0 – level, 1 – pulse.
VSB3V GPIO 14 output mode. 0 – level, 1 – pulse.
VSB3V GPIO 13 output mode. 0 – level, 1 – pulse.
6
5
4
3
2
VSB3V GPIO 12 output mode. 0 – level, 1 – pulse. If this serves as IRQ/SMI#
mode, it will have same function.
1
0
GP11_OMODE R/W
GP10_OMODE R/W
VSB3V GPIO 11 output mode. 0 – level, 1 – pulse.
VSB3V GPIO 10 output mode. 0 – level, 1 – pulse.
7.14 GPIO1x Pulse Width Control Register – Index 14h
Power-on default [7:0] =0000_0000b
Bit
7:2
1:0
Name
Reserved
R/W
PWR
Description
R/W
VSB3V Reserved. Read return 0.
GP1_PSWDTH[1:0 R/W
]
VSB3V GPIO1x pulse width. If set the GPIO1x to pulse mode, the pulse
width can be defined as follows.
00b – 500us (Default)
01b – 1ms
10b – 20ms
11b – 100ms
- 17 -
July, 2007
V0.27P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
