F71872
2’b11
R/W
6-5 VDDLED_SEL
VDDLED function select, powered by VDD.
00: VDDLED always output low.
01: VDDLED tri-state
10: VDDLED output 0.5Hz clock.
11: VDDLED output 1Hz clock.
( clock output is inverse with VSBLED clock output )
(Powered by VDD)
4
3
VDDLED_EN
Reserved
R/W
0
VDDLED enable, powered by VDD.
0: the function of PCIRST5#/GP15/VDDLED is PCIRST5#/GP15.
1: the function of PCIRST5#/GP15/VDDLED is VDDLED.
(Powered by VDD)
-
-
Reserved.
2’b11
2-1 VSBLED_SEL
R/W
VSBLED function select, powered by VSB3V.
00: VSBLED always output low.
01: VSBLED tri-state
10: VSBLED output 0.5Hz clock.
11: VSBLED output 1Hz clock.
(Powered by VSB)
0
VSBLED_EN
R/W
0
VSBLED enable, powered by VSB3V.
0: the function of PWROK2/GP25/VSBLED is PWROK2/GP25.
1: the function of PWROK2/GP25/VSBLED is VSBLED.
(Powered by VSB)
7.1.11 Multi Function Select 1 Register Index 29h (Powered by VDD)
Bit
Name
R/W Default
Description
7
RST_DRV_DIS
R
1
0: enable PCIRSTx pin driving.
1: disable PCIRSTx pin driving.
Power on trap by DTR2#
6-5 Reserved
-
-
Reserved.
30
July, 2007
V0.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
