F71872
7.1.8 UART IRQ Sharing Register Index 26h
Bit
Name
R/W Default
Description
7
CLK24M_SEL
W
0
0: System external clock is 48MHz
1: System external clock is 24MHz
Reserved.
6-2 Reserved
-
-
1
IRQ_MODE
R/W
0
0: PCI IRQ sharing mode (low level).
1: ISA IRQ sharing mode (low pulse).
o
IRQ_SHAR
R/W
0
0: disable IRQ sharing of two UART devices.
1: enable IRQ sharing of two UART devices.
7.1.9 Port Select Register Index 27h
Bit
Name
R/W Default
Description
7-5 Reserved
-
-
-
Reserved.
The default value of the register is power on trap by SOUT1.
4
PORT_4E_EN
W
Pull down to select configuration register port 2E/2F, else 4E/4F.
The port could be changed by writing this register.
0: Configuration register port is 2E/2F.
1: Configuration register port is 4E/4F.
3-0 Reserved
-
-
Reserved.
7.1.10 Power LED Function Select Register Index 28h
Bit
Name
R/W Default
Description
7
Reserved
-
-
Reserved.
29
July, 2007
V0.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
