F71872
7.1.3 Chip ID Register Index 20h
Bit
Name
R/W Default
03h Chip ID 1 of F71872.
Description
Description
Description
Description
Description
7-0 CHIP_ID1
R
7.1.4 Chip ID Register Index 21h
Bit
Name
R/W Default
41h Chip ID2 of F71872.
7-0 CHIP_ID2
R
7.1.5 Vendor ID Register Index 23h
Bit
Name
R/W Default
19h Vendor ID 1 of Fintek devices.
7-0 VENDOR_ID1
R
7.1.6 Vendor ID Register Index 24h
Bit
Name
R/W Default
34h Vendor ID 2 of Fintek devices.
7-0 VENDOR_ID2
R
7.1.7 Software Power Down Register Index 25h
Bit
Name
R/W Default
7-6 Reserved
-
-
Reserved
Power down the KBC device. This will stop the KBC clock.
5
4
SOFTPD_KBC
R/W
0
SOFTPD_HM
R/W
0
Power down the Hardware Monitor device. This will stop the Hardware Monitor
clock.
3
2
1
0
SOFTPD_PRT
SOFTPD_UR2
SOFTPD_UR1
SOFTPD_FDC
R/W
R/W
R/W
R/W
0
0
0
0
Power down the Parallel Port device. This will stop the Parallel Port clock.
Power down the UART 2 device. This will stop the UART 2 clock.
Power down the UART 1 device. This will stop the UART 1 clock.
Power down the FDC device. This will stop the FDC clock.
28
July, 2007
V0.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
