F71862
The PWROK delay timing from VDD3VOK by followed setting
4-3 DELAY
R/W
11
00 : 100ms
01 : 200ms
10 : 300ms
11 : 400ms
2
1
0
VINDB_EN
R/W
R/W
R/W
1
0
0
Enable the PCIRSTIN_N and ATXPWGD de-bounce.
PCIRST_DB_EN
Reserved
Enable the LRESET_N de-bounce.
Dummy register.
ACPI Control Register Index F7h
Bit Name R/W Default
Description
7-4 Reserved
3-2 Reserved
R/W
R/W
R/W
R/W
0
0
0
1
Reserved.
Dummy registers.
1
0
PWR_STS2_TRI
PWR_STS_EN
Set this bit to one will cuase Pin55 be tri-state Status in S5 state.
Enable power status pins. Pin77 will be S5# function. P56 will be ST1 function.
P55 will be ST2 function.
100
July, 2008
V.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
