F71862
+3.3V
Delay
RSTCON#
LRESET#
PCIRST1~3#
PWROK
ATXPG
RSTCON#
So far as the PWROK issue is as the figure above. PWROK is delayed 400ms (default) as
VCC arrives 2.8V, and the delay timing can be programmed by register. (100ms ~ 400ms)
In the figure, the RSTCON# will be implemented by register RSTCON_EN. If RSTCON_EN
be set to 0, the RSTCON# pin will affect PWROK outputs(Default). If RSTCON_EN be set to 1,
the RSTCON# pin will affect PCIRST outputs.
VCC3
CPU
1
3
2
4
1K-8P4R
1K-8P4R
NORTH BRIDGE
PCIRST3#
PCIRST2#
IDE
PCIRST3#
PCIRST2#
ATA 133
VSB3
FRONT PANEL
VSB3
SATA*2
R86
SOUTH BRIDGE
4.7K
-PWR_BTN
2
R85
5
7
6
8
1
RSTGND
RESET
PSW+
PSW-
4.7K R88
1
2
R87
C47
33
0.1UF
Front Panel
RSTCON#
LRESET#
PWSIN#
F71862
ATXPG_IN
PSON#
PCI
VSB3
VCC3
S3#
1
3
2
4
2
4.7K
4.7K
PWSOUT#
RSMRST#
PCIRST1#
1
1K
VSB5
R90
ATX1
3V3
4.7K
11
1
VCC3
VCC5
3V3
3V3
12
13
14
15
16
17
18
19
20
2
VSB5
-12V
-12V
GND
PS-ON
GND
GND
GND
-5V
3
GND
5V
4
5
R91
4.7K
GND
5V
6
7
GND
PW-OK
5VSB
12V
8
9
VCC5
VSB5
5V
10
Title
+12V
5V
Feature Integration Technology Inc.
ATX CONNECTOR
ATX CONNECTOR
TC1
22uF
Size
A
Document Number
Example_ACPI
Rev
0.10
Date:
Tuesday , May 16, 2006
Sheet
7
of
7
ACPI Reference Circuit
Status Pins Application
The F71862 provides two status pins (ST1/ST2) and S5 signal for user application. The state
65
July, 2008
V.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
