F71862
7-5 ECP_MODE
R/W
000 000: SPP Mode.
001: PS/2 Parallel Port Mode.
010: Parallel Port Data FIFO Mode.
011: ECP Parallel Port Mode.
100: EPP Mode.
101: Reserved.
110: Test Mode.
111: Configuration Mode.
Only valid in ECP.
4
3
2
ERRINTR_EN
DAMEN
R/W
R/W
R/W
0
0
1
0: disable the interrupt generated on the falling edge of ERR#.
1: enable the interrupt generated on the falling edge of ERR#.
0: disable DMA.
1: enable DMA. DMA starts when SERVICEINTR is 0.
SERVICEINTR
0: enable the following case of interrupt.
DMAEN = 1: DMA mode.
DMAEN = 0, DIR = 0: set to 1 whenever there are writeIntrThreshold or more
bytes are free in the FIFO.
DMAEN = 0, DIR = 0: set to 1 whenever there are readIntrThreshold or more
bytes are valid to be read in the FIFO.
1
0
FIFOFULL
R
R
0
0
0: The FIFO has at least 1 free byte.
1: The FIFO is completely full.
FIFOEMPTY
0: The FIFO contains at least 1 byte.
1: The FIFO is completely empty.
7.5 Keyboard Contoller
The KBC circuit provides the functions included a keyboard and/or a PS/2 mouse, and
can be used with IBM-compatible personal computers or PS/2-based systems. The
controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the
data, and presents the data to the system as a byte of data in its output buffer. The controller
will assert an interrupt to the system when data are placed in its output buffer.
Output Buffer
The output buffer is an 8-bit read-only register at I/O address 60H. The keyboard
controller uses the output buffer to send the scan code received from the keyboard and data
bytes required by commands to the system.
Input Buffer
The input buffer is an 8-bit write-only register at I/O address 60H or 64H. Writing to
address 60H sets a flag to indicate a data write; writing to address 64H sets a flag to
indicate a command write. Data written to I/O address 60H is sent to keyboard through the
39
July, 2008
V.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
