F71862
Parallel Port Data Register Base + 0
Bit
Name
R/W Default
Description
7-0 DATA
R/W 00h The output data to drive the parallel port data lines.
ECP Address FIFO Register Base + 0
Bit Name R/W Default
7-0 ECP_AFIFO
Description
Access only in ECP Parallel Port Mode and the ECP_MODE programmed in
the Extended Control Register is 011.
R/W
00h
The data written to this register is placed in the FIFO and tagged as an
Address/RLE. It is auto transmitted by the hardware. The operation is only
defined for forward direction. It divide into two parts :
Bit 7 :
0: bits 6-0 are run length, indicating how many times the next byte to appear (0
= 1time, 1 = 2times, 2 = 3times and so on).
1: bits 6-0 are a ECP address.
Bit 6-0 :
Address or RLE depends on bit 7.
Device Status Register Base + 1
Bit
Name
R/W Default
Description
7
6
5
4
3
BUSY_N
R
R
R
R
R
R
R
-
-
Inverted version of parallel port signal BUSY.
Version of parallel port signal ACK#.
Version of parallel port signal PE.
ACK_N
PERROR
SELECT
ERR_N
-
-
Version of parallel port signal SLCT.
Version of parallel port signal ERR#.
Reserved. Return 11b when read.
-
2-1 Reserved
TMOUT
11
-
0
This bit is valid only in EPP mode. Return 1 when in other modes.
It indicates that a 10uS time out has occurred on the EPP bus.
0: no time out error.
1: time out error occurred, write 1 to clear.
Device Control Register Base + 2
Bit Name R/W Default
7-6 Reserved
Description
-
11
0
Reserved. Return 11b when read.
5
DIR
R/W
0: the parallel port is in output mode.
1: the parallel port is in input mode.
It is auto reset to 0 when in SPP mode.
4
3
ACKIRQ_EN
SLIN
R/W
R/W
0
0
Enable an interrupt at the rising edge of ACK#.
Inverted and then drives the parallel port signal SLIN#.
When read, the status of inverted SLIN# is return.
36
July, 2008
V.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
