F71869A
definition of this pin in ECP and EPP mode.
Default General Purpose IO.
GPIO67
I/OOD12t,5v
I/O12st,5v
Parallel port data bus bit 0. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP
mode.
PD0
109
3VCC
GPIO70
I/OOD12t,5v
Default General Purpose IO.
I/O12st,5v
I/OOD12t,5v
I/O12st,5v
Parallel port data bus bit 1.
Default General Purpose IO.
Parallel port data bus bit 2.
Default General Purpose IO.
Parallel port data bus bit 3.
Default General Purpose IO.
Parallel port data bus bit 4.
Default General Purpose IO.
Parallel port data bus bit 5.
Default General Purpose IO.
Parallel port data bus bit 6.
Default General Purpose IO.
Parallel port data bus bit 7.
Default General Purpose IO.
PD1
110
111
112
113
114
115
116
3VCC
3VCC
3VCC
3VCC
3VCC
3VCC
3VCC
GPIO71
PD2
GPIO72
I/OOD12t,5v
I/O12st,5v
PD3
GPIO73
I/OOD12t,5v
I/O12st,5v
PD4
GPIO74
I/OOD12t,5v
I/O12st,5v
PD5
GPIO75
I/OOD12t,5v
I/O12st,5v
PD6
GPIO76
I/OOD12t,5v
I/O12st,5v
PD7
GPIO77
I/OOD12t,5v
4.6 Hardware Monitor
Pin No.
Pin Name
Type
PWR
Description
Voltage input 6. This pin support OVP function, and default
is disable.
I_VSB3V
93
VIN6
AIN
Voltage input 5. This pin support OVP function, and default
is disable.
I_VSB3V
I_VSB3V
94
95
VIN5
AIN
AIN
Voltage input 4 or VDIMM input used in AMD platform. The
input voltage level for timing control usage must be over 1V
after voltage divider.
VIN4 (VDIMM)
Voltage input 3 or VDDA input used in AMD platform. The
input voltage level for timing control usage must be over 1V
after voltage divider.
I_VSB3V
I_VSB3V
96
97
VIN3 (VDDA)
VIN2 (VLDT)
AIN
AIN
Voltage input 2 or VLDT input used in AMD platform. The
input voltage level for timing control usage must be over 1V
after voltage divider.
Voltage Input for Vcore. The input voltage level for timing
control usage must be over 0.7V.
I_VSB3V
3VCC
98
21
VIN1 (Vcore)
FANIN1
AIN
INst, 5v
Fan 1 tachometer input.
Fan 1 control output. It is also a trap pin to select a PWM or
a DAC output, except being an output pin. It defaults to be
a voltage output by pulling down 100k internally. It is set as
a PWM output as connected a 4.7K resistor and pulled
high to 3.3V.
OOD12,5v
AOUT
22
23
FANCTL1
FANIN2
3VCC
3VCC
INst, 5v
Fan 2 tachometer input.
17
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
