F71869A
as VSB drops to 2.6V. There is an option to set RSMRST#
rises at 3.05V and falls at 2.95V.
Case Open Detection #. This pin is connected to a
specially designed low power CMOS flip-flop backed by
the battery for case open state preservation during power
loss.
87
COPEN#
INst,5v
VBAT
4.8 Power Saving and Others
Pin No.
Pin Name
Type
PWR
Description
Wake-up event input. The signal input wakes the system
up from the sleep state.
I_VSB3V
42
EVENT_IN0#
INts , 5 v
Standby power rail control pin 0. This pin controls an
external PMOS to turn on or off the standby power rail. In
the S5 state, the default is set to 1 to cut off the standby
power rail.
I_VSB3V
I_VSB3V
43
44
ERP_CTRL0#
ERP_CTRL1#
DPWROK
OD12
OD12
Standby power rail control pin 1. This pin controls an
external PMOS to turn on or off the standby power rail. In
the S5 state, the default is set to 1 to cut off the standby
power rail.
Resume Reset# function, It is power good signal of VSB,
which is delayed 66ms as VSB arrives at 4.4V. Couple this
pin to PCH when system supports Intel DSW state
function.
OD12,5v
I_VSB3V
I_VSB3V
46
47
Active high. Timing sequence 3 of power on/off sequence
pins. The external pull high resistor is required.
(Detected by VIN3 level good)
TIMING_3
SLP_SUS#
TIMING_4
OD12,5v
For Intel CPT DSW function. Connect to PCH SLP_SUS
pin.
INst,lv
Active high. Timing sequence 4 of power on/off sequence
pins. The external pull high resistor is required.
(Detected by VIN1 level good)
OD12,5v
CIRWB#
GPIO01
CIRTX#
GPIO02
CIRRX#
GPIO03
INst,5v
I/OOD12t
O20
CIR wide-band receiver input. (For Learning use)
General Purpose IO. GPIO function is selected by register
setting
I_VSB3V
I_VSB3V
49
50
CIR Transmitter to transmit data.
General Purpose IO. GPIO function is selected by register
setting
I/OOD12t
INs t. 5 v
CIR long-range receiver input
I_VSB3V
I_VSB3V
51
52
General Purpose IO. GPIO function is selected by register
setting
I/OOD12t
Strap Pin for AMD and Intel Cougar Point timing. Internal
pull high with AMD timing (Default).
STRAP_TIMING
SUS_ACK#
INst,5v
This pin must wait SUS_WARN# signal for entering DSW
power state.
OOD16,5v
I_VSB3V
53
Active high. Timing sequence 2 of power on/off sequence
pins. The external pull high resistor is required.
(Detected by VIN4 level good)
TIMING_2
OD12,5v
20
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
