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F71869AD 参数 Datasheet PDF下载

F71869AD图片预览
型号: F71869AD
PDF下载: 下载PDF文件 查看货源
内容描述: 超级I / O +硬件监控 [Super I/O + Hardware Monitor]
分类和应用: 监控
文件页数/大小: 156 页 / 1561 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F71869A  
When GPIO51 is in input mode, set this bit to select which input event  
should be detected.  
0: rising edge  
1: falling edge  
1
0
GPIO51_DET_SEL R/W  
GPIO50_DET_SEL R/W  
0
0
When GPIO50 is in input mode, set this bit to select which input event  
should be detected.  
0: rising edge  
1: falling edge  
6.8.35 GPIO5 Event Status Register Index A6h  
Bit  
Name  
R/W Default  
Description  
When GPIO37 is in input mode and a GPIO37 input is detected  
according to CRA5[7], this bit will be set to 1. Write a 1 to this bit will  
clear it to 0.  
GPIO37_  
EVENT_STS  
7
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
-
-
-
-
-
-
-
-
When GPIO36 is in input mode and a GPIO36 input is detected  
according to CRA5[6], this bit will be set to 1. Write a 1 to this bit will  
clear it to 0.  
GPIO36_  
EVENT_STS  
6
5
4
3
2
1
0
When GPIO35 is in input mode and a GPIO35 input is detected  
according to CRA5[5], this bit will be set to 1. Write a 1 to this bit will  
clear it to 0.  
GPIO35_  
EVENT_STS  
When GPIO54 is in input mode and a GPIO54 input is detected  
according to CRA5[4], this bit will be set to 1. Write a 1 to this bit will  
clear it to 0.  
GPIO54_  
EVENT_STS  
When GPIO53 is in input mode and a GPIO53 input is detected  
according to CRA5[3], this bit will be set to 1. Write a 1 to this bit will  
clear it to 0.  
GPIO53_  
EVENT_STS  
When GPIO52 is in input mode and a GPIO52 input is detected  
according to CRB5[2], this bit will be set to 1. Write a 1 to this bit will  
clear it to 0.  
GPIO52_  
EVENT_STS  
When GPIO51 is in input mode and a GPIO51 input is detected  
according to CRB5[1], this bit will be set to 1. Write a 1 to this bit will  
clear it to 0.  
GPIO51_  
EVENT_STS  
When GPIO50 is in input mode and a GPIO50 input is detected  
according to CRB5[0], this bit will be set to 1. Write a 1 to this bit will  
clear it to 0.  
GPIO50_  
EVENT_STS  
6.8.36 GPIO5 KBC Emulation Control Register 1Index A9h  
Bit  
Name  
R/W Default  
Description  
The delay time for repeat make code.  
00: 500ms ~ 750ms.  
01: 750ms ~ 1000ms.  
10: 1000ms ~ 1250ms.  
11: 1250ms ~ 1500ms.  
7-6  
DELAY_TIME  
R/W  
R/W  
00  
00  
The make code repeat time select.  
00: 50ms.  
01: 100ms.  
5-4  
REP_TIME  
10: 250ms.  
11: 500ms.  
124  
Oct., 2011  
V0.19P  
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