F71869A
0: GPIO40 is open drain in output mode.
1: GPIO40 is push pull in output mode.
0
GPIO40_DRV_EN R/W
0
6.8.27 GPIO4 PME Enable Register ⎯ Index B4h
Bit
Name
R/W Default
Description
7-4
Reserved
-
-
Reserved
When GPIO43_EVENT_STS is 1 and GPIO43_PME_EN is set to 1, a
GPIO PME event will be generated.
3
2
1
0
GPIO43_PME_EN R/W
GPIO42_PME_EN R/W
GPIO41_PME_EN R/W
GPIO40_PME_EN R/W
0
When GPIO42_EVENT_STS is 1 and GPIO42_PME_EN is set to 1, a
GPIO PME event will be generated.
0
0
0
When GPIO41_EVENT_STS is 1 and GPIO41_PME_EN is set to 1, a
GPIO PME event will be generated.
When GPIO40_EVENT_STS is 1 and GPIO40_PME_EN is set to 1, a
GPIO PME event will be generated.
6.8.28 GPIO4 Input Detection Select Register ⎯ Index B5h
Bit
Name
R/W Default
Description
7-4
Reserved
-
-
Reserved
When GPIO43 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
3
2
1
0
GPIO43_DET_SEL R/W
GPIO42_DET_SEL R/W
GPIO41_DET_SEL R/W
GPIO40_DET_SEL R/W
0
When GPIO42 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
0
0
0
When GPIO41 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
When GPIO40 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
6.8.29 GPIO4 Event Status Register ⎯ Index B6h
Bit
Name
R/W Default
Description
7-4
Reserved
-
-
Reserved
When GPIO43 is in input mode and a GPIO43 input is detected
according to CRB5[3], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
GPIO43_
EVENT_STS
3
2
R/W
-
When GPIO42 is in input mode and a GPIO42 input is detected
according to CRB5[2], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
GPIO42_
EVENT_STS
R/W
-
121
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
