F71869A
When GPIO41 is in input mode and a GPIO41 input is detected
according to CRB5[1], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
GPIO41_
EVENT_STS
1
0
R/W
R/W
-
-
When GPIO40 is in input mode and a GPIO40 input is detected
according to CRB5[0], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
GPIO40_
EVENT_STS
6.8.30 GPIO5 Output Enable Register ⎯ Index A0h
Bit
Name
R/W Default
Description
7-5
Reserved
-
-
Reserved.
0: GPIO54 is in input mode.
1: GPIO54 is in output mode.
4
3
2
1
0
GPIO54_OE
GPIO53_OE
GPIO52_OE
GPIO51_OE
GPIO50_OE
R/W
0
0: GPIO53 is in input mode.
1: GPIO53 is in output mode.
R/W
R/W
R/W
R/W
0
0
0
0
0: GPIO52 is in input mode.
1: GPIO52 is in output mode.
0: GPIO51 is in input mode.
1: GPIO51 is in output mode.
0: GPIO50 is in input mode.
1: GPIO50 is in output mode.
6.8.31 GPIO5 Output Data Register ⎯ Index A1h
Bit
Name
R/W Default
Description
7-5
Reserved
-
-
Reserved.
0: GPIO54 outputs 0 when in output mode.
1: GPIO54 outputs 1 when in output mode.
4
3
2
1
0
GPIO54_VAL
GPIO53_VAL
GPIO52_VAL
GPIO51_VAL
GPIO50_VAL
R/W
1
0: GPIO53 outputs 0 when in output mode.
1: GPIO53 outputs 1 when in output mode.
R/W
R/W
R/W
R/W
1
1
1
1
0: GPIO52 outputs 0 when in output mode.
1: GPIO52 outputs 1 when in output mode.
0: GPIO51 outputs 0 when in output mode.
1: GPIO51 outputs 1 when in output mode.
0: GPIO50 outputs 0 when in output mode.
1: GPIO50 outputs 1 when in output mode.
6.8.32 GPIO5 Pin Status Register ⎯ Index A2h
Bit
Name
R/W Default
Description
7-5
Reserved
-
-
Reserved.
4
3
2
1
0
GPIO54_IN
GPIO53_IN
GPIO52_IN
GPIO51_IN
GPIO50_IN
R
R
R
R
R
-
-
-
-
-
The pin status of DSKCHG#/GPIO54.
The pin status of WPT#/GPIO53.
The pin status of INDEX#/GPIO52.
The pin status of TRK0#/GPIO51.
The pin status of RDDATA#/GPIO50.
122
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
