MC81F4432
19.2 Timer 2 8-Bit Mode
T2CS
T2OVIE
fxx/1024
fxx/256
fxx/64
fxx/16
fxx/8
Timer 2 overflow INT enable
Data BUS
8
OVF
T2OVIR
T2 Overflow
Interrupt
Timer 2 Overflow INT request
M
U
X
fxx/4
fxx/2
fxx/1
fxt
T2OVIF
8-Bit Up Counter
(Read - only)
Clear
T2CC
Match signal
R
Clear
T2CR
T2MIE
EC2
Timer 2 match INT enable
Counter stop
Match
8-Bit Comparator
T2MIR
T2 Match
Interrupt
Timer 2 Match INT request
T2O
M
U
X
T2MIF
EXT5
Timer 2 Buffer Register
Timer 2 Data Register
T2CC
Overflow signal
Match signal
EINT0H
T2DR
8
EXT5
Interrupt
Data BUS
Figure 19-1 8-bit Timer 2 Block Diagram
Timer 2 has the following functional components:
-
-
-
-
-
-
Clock frequency divider (fxx divided by 1024, 256, 64, 16, 8, 4, 2, 1, fxt) with multiplexer
External clock input pin, EC2 (R06)
I/O pins for capture input, EXT5 (R07) or match output T2O (R07)
8-bit counter (T2CR), 8-bit comparator, and 8-bit reference data register (T2DR)
Timer 2 status and control register (T2SCR)
Timer 2 overflow interrupt and match interrupt generation
October 19, 2009 Ver.1.35
129
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