MC81F4432
T3SCR
TIMER 3 STATUS AND CONTROL REGISTER (T3SCR)
00D3H
To enable the timer 3 match interrupt, you must set “1” to T3MIE.
When the timer 3 match interrupt sub-routine is serviced, the timer 1 match interrupt request flag bit,
T3MIR(IRQH.1), is automatically cleared.
To enable the timer 3 overflow interrupt, you must set “1” to T3OVIE.
When the timer 3 overflow interrupt sub-routine is serviced, the timer 3 overflow interrupt request flag
bit, T3OVIR(IRQH.0), is automatically cleared.
7
–
–
6
–
–
5
4
3
2
1
0
T3SCR
T3MS T3CC
R/W R/W
T3CS
Reset value:
--00_0000b
R/W
R/W
R/W
R/W
–
bit7 – bit6
Not used for MC81F4x32
0: Interval mode
T3MS
Timer 3 Mode Selection Bit
1: Capture mode (OVF can occur)
0: No effect
1: Clear the Timer 3 counter (When
write, automatically cleared “0” after
being cleared counter)
T3CC
Timer 3 Counter Clear Bit
0000: Counter stop
0001: Not available
0010: Not available
0011: Not available
0100: Not available
0101: External clock (EC3) rising edge
0110: External clock (EC3) falling edge
0111: fxt ( sub clock )
1000: fxx/2
T3CS
Timer 3 Clock Selection Bits
1001: fxx/4
1010: fxx/8
1011: fxx/16
1100: fxx/32
1101: fxx/128
1110: fxx/512
1111: fxx/2048
Note :
You must set the T3CC(T3SCR.4) bit after set T3DR register. The timer 3 counter value is
compared with timer 3 buffer register instead of T3DR. And T3DR value is copied to timer 3
buffer.
October 19, 2009 Ver.1.35
127
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