MC81F4432
T2SCR
TIMER 2 STATUS AND CONTROL REGISTER (T2SCR)
00B6H
To enable the timer 2 match interrupt, you must set “1” to T2MIE.
When the timer 2 match interrupt sub-routine is serviced, the timer 1 match interrupt request flag bit,
T2MIR(IRQH.3), is automatically cleared.
To enable the timer 2 overflow interrupt, you must set “1” to T2OVIE.
When the timer 2 overflow interrupt sub-routine is serviced, the timer 2 overflow interrupt request flag
bit, T2OVIR(IRQH.2), is automatically cleared.
7
6
5
4
3
2
1
0
T2MOD
–
T2MS T2CC
R/W R/W
T2CS
T2SCR
Reset value: 00H
R/W
–
R/W
R/W
R/W
R/W
0: Two 8-bit timers mode (Timer 2/3)
1: One 16-bit timer mode (Timer 2)
Not used for MC81F4x32
0: Interval mode (T2O)
T2MOD
–
Timer 2 mode Selection Bit
bit6
T2MS
Timer 2 Mode Selection Bit
1: Capture mode (OVF can occur)
0: No effect
1: Clear the Timer 2 counter (When
write, automatically cleared “0” after
being cleared counter)
T2CC
Timer 2 Counter Clear Bit
0000: Counter stop
0001: Not available
0010: Not available
0011: Not available
0100: Not available
0101: External clock (EC2) rising edge
0110: External clock (EC2) falling edge
0111: fxt ( sub clock )
1000: fxx/1
T2CS
Timer 2 Clock Selection Bits
1001: fxx/2
1010: fxx/4
1011: fxx/8
1100: fxx/16
1101: fxx/64
1110: fxx/256
1111: fxx/1024
Note :
You must set the T2CC(T2SCR.4) bit after set T2DR register. The timer 2 counter value is
compared with timer 2 buffer register instead of T2DR. And T2DR value is copied to timer 2
buffer.
October 19, 2009 Ver.1.35
125
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