MC81F4432
18.3 Timer 1 8-Bit Mode
T1CS
T1OVIE
fxx/1024
fxx/256
fxx/64
fxx/16
fxx/8
Timer 1 overflow INT enable
Data BUS
8
OVF
T1OVIR
T1 Overflow
Interrupt
Timer 1 Overflow INT request
M
U
X
fxx/4
fxx/2
fxx/1
fxt
T1OVIF
T1CC
Match signal
8-Bit Up Counter
(Read - only)
Clear
R
Clear
T1CR
T1MIE
EC1
Timer 1 INT enable
M
U
X
Counter stop
Match
T1MIR
8-Bit Comparator
T1 Match
Interrupt
Timer 1 Match INT request
T1O/PWM1O
M
U
X
EXT3
T1MIF
T1MS
Timer 1 Buffer Register
Timer 1 Data Register
T1CC
Overflow signal
Match signal
EINT0L
T1DR
8
EXT3
Interrupt
Data BUS
Figure 18-2 8-bit Timer 1 Block Diagram
Timer 1 has the following functional components:
-
-
-
-
-
-
Clock frequency divider (fxx divided by 1024, 256, 64, 16, 8, 4, 2, 1, fxt) with multiplexer
External clock input pin, EC1 (R04)
I/O pins for capture input, EXT3 (R05) or PWM or match output PWM1O/T1O (R05)
8-bit counter (T1CR), 8-bit comparator, and 8-bit reference data register (T1DR)
Timer 1 status and control register (T1SCR)
Timer 1 overflow interrupt and match interrupt generation
October 19, 2009 Ver.1.35
119
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