MC81F4432
Function Description
Interval Timer Mode
A match signal is generated and T0O pins are toggled when the T0CR register value equals the
T0DR register value. The match signal generates a timer match interrupt and clears the T0CR
register.
Pulse Width Modulation Mode
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output
at the PWM0O pin. As in interval timer mode, a match signal is generated when the counter value is
identical to the value written to the T0DR register. In PWM mode, however, the match signal does not
clear the counter. Instead, it runs continuously, overflowing at FFH, and then continues incrementing
from 00H.
Although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not
typically used in PWM-type applications. Instead, the pulse at the PWM0O pin is held to Low level as
long as the reference data value is less than or equal to ( ) the counter value and then the pulse is
held to High level for as long as the data value is greater than ( > ) the counter value. One pulse width
is equal to t
* 256.
CLK
So, the period and duty times are,
Duty = t
Period = t
* (T0DR + 1)
* 256
CLK
CLK
In order to generate the PWM0O signal, 3 steps are required,
Steps
Example C code
T0CONM = 0x03;
T0DR = 25;
T0SCR = 0x38;
Make sure the PWM0O port is set by PWM output mode
Set the T0DR value properly
Set the T0SCR register properly
Capture Mode
In capture mode, you have to set EXT1 interrupt. When the EXT1 interrupt is occurred, the T0CR
register value is loaded into the T0DR register and the T0CR register is cleared.
And the timer 0 overflow interrupt is generated whenever the T0CR value is overflowed.
So, If you count how many overflow is occurred and read the T0DR value in EXT1 interrupt routine, it
is possible to measure the time between two EXT1 interrupts. Or it is possible to measure the time
from the T0 initial time to the EXT1 interrupt occurred time.
The time = ( 256 * tCLK ) * overflow_count + (tCLK * T0DR)
Note
„t ‟ is the period time of the timer-counter‟s clock source
CLK
You must set the T0DR value before set the T0SCR register. Because T0DR value is
fetched when the count is started(the T0CC bit is set) or match/overflow event is occurred.
October 19, 2009 Ver.1.35
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