CMS4A16LAx–75Ex
FUNCTIONAL DESCRIPTION
Initialization
The Fidelix 128Mb SDRAM is a quad-bank DRAM that
operates at 1.8V or 2.5V and includes a synchronous inter-
face (all signals are registered on the positive edge of the clock
signal, CLK ).
SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those specified
may result in undefined operation. Once power is applied to
VDD and VDDQ(simultaneously) and the clock is stable (meets
the clock specifications in the AC characteristics), the SDRAM
requires a 100µs delay prior to issuing any command other than
a COMMAND INHIBIT or NOP. The COMMAND INHIBIT or
NOP should be applied at least once during the 100µs delay.
After the 100µs delay, a PRECHARGE command should be
applied. All banks must then be precharged, thereby placing the
device in the all banks idle state. Once in the idle state, two
AUTO REFRESH cycles must be performed. After the AUTO
REFRESH cycles are complete, the SDRAM is ready for mode
register programming. Because the mode register will power up
in an unknown state, it should be loaded prior to applying any
operational command. Refer Figure 1.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command.
The address bits registered coincident with the ACTIVE
command are used to select the bank and row to be
accessed (BA0 and BA1 select the bank, A0- A11 select the
row). The address bits (A0-A8) registered coincident with the
READ or WRITE command are used to select the starting
column location for the burst access.The SDRAM must be ini-
tialized prior to normal operation. The following sections pro-
vide detailed information regarding device initialization,
register definition, command descriptions and device operation.
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Rev. 0.5, May. ‘07
FIDELIX [ FIDELIX ]
