CMS4A16LAx–75Ex
Pin Description
Symbol
Type
Description
Clock : CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
edge of CLK. CLK also increments the internal burst counter and controls the output registers.
CLK
Input
Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. Deactivating the
clock provides PRECHARGE POWER-DOWN and SELF Refresh operation(all banks idle),
ACTIVE POWER-DOWN(row active in any bank) or CLOCK SUSPEND operation(burst/access
in progress). CKE is synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers,
including CLK, are disabled during power-down and self refresh modes, providing low standby
power. CKE may be tied HIGH.
CKE
Input
Chip Select: /CS enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when /CS is registered HIGH. /CS provides for external
bank selection on systems with multiple banks. /CS is considered part of the command code.
/CS
Input
Input
Command Inputs : /CAS, /RAS, and /WE (along with /CS) define the command being entered.
/CAS, /RAS, /WE
Input/Output Mask: L(U)DQM is sampled HIGH and is an input mask signal for write accesses
and an output disable signal for read accesses. Input data is masked during a WRITE cycle. The
output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle.
LDQM corresponds to DQ0 – DQ7 and UDQM corresponds to DQ8–DQ15.
LDQM, UDQM
BA0, BA1
Input
Input
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied. These pins also provide the op-code during a LOAD
MODE REGISTER command.
Address Inputs: A0–A11 are sampled during the ACTIVE command (row- address A0–A11)
and READ/WRITE command (column-address A0–A8; with A10 defining auto precharge) to
select one location out of the memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank
selected by BA0, BA1 (A10 LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
A0-A11
Input
DQ
NC
I/O
Data Input/Output : Data bus
-
No Connect
VDDQ
VSSQ
VDD
VSS
Supply
Supply
Supply
Supply
DQ Power: Provide isolated power to DQs for improved noise immunity.
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Power Supply: Voltage dependant on option.
Ground.
5
Rev. 0.5, May. ‘07
FIDELIX [ FIDELIX ]
