CMS4A16LAx–75Ex
128M(8Mx16) Low Power SDRAM
Features
- Functionality
- LVCMOS Compatible IO Interface
- 54ball FBGA with 0.8mm ball pitch
- CMS4A16LAF : Normal
- Standard SDRAM Functionality
- Programmable burst lengths : 1, 2, 4, 8, or full page
- JEDEC Compatibility
- CMS4A16LAG : Pb-Free
- CMS4A16LAH : Pb-Free & Halogen Free
- Low Power Features
- Low voltage power supply : 1.8V
- Auto TCSR(Temperature Compensated Self Refresh)
- Partial Array Self Refresh power-saving mode
- Deep Power Down Mode
- Driver Strength Control
- Operating Temperature Ranges:
- Special (-10℃ to +60℃)
- Commercial (0℃ to +70℃)
- Extended (-25℃ to +85℃)
- Industrial (-40℃ to +85℃)
Functional Description
The CMS4A16LAF Family is high-performance CMOS Dynamic
RAMs (DRAM) organized as 8M x 16. These devices feature
advanced circuit design to provide low active current and
extremely low standby current.
The device is compatible with the JEDEC standard
LP-SDRAM specifications.
Logic Block Diagram
Bank 3
Bank 2
CKE
CLK
Bank 1
/CS
/WE
/CAS
/RAS
Control
Logic
Refresh
Counter
Bank 0
Bank 0
LDQM -
UDQM
Bank 0
Row
Memory
Array
Row
Address
Row
Address
Mux
Addr
Latch/
Mode
Register
Data
Latch/
Decoder
Decoder
Output
Register
8Kx4K
Extended
Mode
Register
Sense Amp
Bank
Control
Logic
Write Drivers
DQM Mask
DQ0 -
DQ15
A0-A11
BA0-BA1
Address
Register
Column
Column
Decoder
Data
Input
Register
Column
Decoder
Column
Decoder
Column
Address
Latch
Decoder
Selection Guide
Voltage
Access Time(tAC)
Device
Frequency
tRCD
tRP
VDD
VDDQ
CL=2
CL=3
7ns
133MHz
100MHz
20ns
20ns
20ns
20ns
CMS4A16LAx-75Ex
1.7-1.95V
1.7-VDD
8ns
3
Rev. 0.5, May. ‘07
FIDELIX [ FIDELIX ]
