AN-6920
APPLICATION NOTE
By increasing
V
RO
(i.e. the turns ratio,
n
), the capacitive
switching loss and conduction loss of the MOSFET are
reduced. This also reduces the voltage stress of the
secondary-side rectifier.
V
RO
should be determined by a
trade-off between the hold-up time and voltage stresses of
the secondary-side rectifier diode.
output capacitor effects the hold-up time. The minimum
PFC output voltage for required hold-up time is obtained as:
V
O
.
PFC
min
≥
2
⋅
t
HOLD
⋅
P
OUT
2
+
V
O
.
PFC
.
HLD
η
⋅
C
O
.
PFC
(
18
)
where:
t
HOLD
is the required holdup time;
P
OUT
is total nominal output power;
V
O.PFC.L
is the minimum PFC output voltage for required
hold-up time; and
V
O.PFC.HLD
is the allowable minimum PFC output voltage
during the hold-up time.
The voltage of transformer primary-side winding is clamped
to V
O,PFC
, so the minimum PFC output voltage during the
hold-up time is obtained as:
V
O
.
PFC
.
HLD
=
n
⋅
(
V
O
+
V
F
)
(
19
)
where V
F
is the synchronous rectification MOSFET drain-
to-source diode forward voltage, V
F
, about 1V.
(Design Example)
Because the PFC response is very slow,
the hold-up time needs to be more than 12ms to avoid PFC
output voltage drop effecting the output voltage at
dynamic-load condition. Assuming hold-up time is 12ms,
the V
O.PFCmin
as:
V
O
.
PFC
=
Figure 13. Typical Waveforms of QR Flyback Converter
min
≥
2
⋅
t
HOLD
⋅
P
OUT
+
[
n
⋅
(
V
O
+
V
F
)]
2
η
⋅
C
O
.
PFC
2
⋅
12
×
10
−
3
×
90
+
[12
⋅
(19
+
1)]
2
=
286
V
−
6
0.9
⋅
100
×
10
Assuming 75V MOSFET
(synchronous rectification) is used for secondary side,
with 70% voltage margin:
(Design
Example)
V
O
.
PFC
n
V
O
.
PFC
400
∴
n
>
=
=
11.94
0.7
⋅
75
−
V
O
0.7
⋅
75
−
19
0.7
⋅
75
>
V
D
nom
=
V
O
+
[STEP-B3] Transformer Design
Figure 14 shows the typical switching timing of a quasi-
resonant converter. The sum of MOSFET conduction time
(t
ON
), diode conduction time (t
D
), and drain voltage falling
time (t
F
) is the switching period (t
S
). To determine the
primary-side inductance (L
m
), the following parameters
should be determined first.
Minimum Switching Frequency (f
S.QRmin
)
The minimum switching frequency occurs at the minimum
input voltage and full-load condition, which should be
higher than 20kHz to avoid audible noise. By increasing
f
S.QRmin
, the transformer size can be reduced. However, this
results in increased switching losses. Determine
f
S.QRmin
by a
trade-off between switching losses and transformer size.
Typically
f
S.QRmin
is set around 70kHz.
Thus, n is determined as 12.
[STEP-B2] Calculate the Minimum PFC Output
Voltage (V
O.PFC.L
) for Hold-up Time
For the PFC output capacitor, it is typical to use 0.5~1 F
per 1W output power for 400V PFC output. Meanwhile, it is
reasonable to use ~1 F per 1W output power for variable
output PFC due to the larger voltage drop during the hold-
up time than 400V output. In this example, two 100 F
capacitors are selected for the output capacitors (C
O.PFC
).
Lower PFC output voltage can improve system efficiency at
low AC line voltage condition, but the energy of the PFC
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
Falling Time of the MOSFET Drain Voltage
(t
F
)
As shown in Figure 14, the MOSFET drain voltage fall time
is half of the resonant period of the MOSFET’s effective
output capacitance and primary-side inductance. The typical
value for t
F
is 0.6~1.2 s.
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