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PC817 参数 Datasheet PDF下载

PC817图片预览
型号: PC817
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的临界模式PFC /准谐振电流模式PWM控制器 [Integrated Critical-Mode PFC / Quasi-Resonant Current-Mode PWM Controller]
分类和应用: 光电功率因数校正输出元件控制器
文件页数/大小: 17 页 / 676 K
品牌: FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
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AN-6920
APPLICATION NOTE
(Design Example)
0
.
7
>
30
µ
A
,
R
DET
2
<
23
.
3
k
R
DET
2
[STEP-B4] Design the Feedback Circuit
Figure 19 is a typical feedback circuit mainly consisting of a
shunt regulator and a photo-coupler. R
01
and R
02
form a
voltage divider for output voltage regulation. R
F
and C
F
are
adjusted for control-loop compensation. A small-value RC
filter (e.g. R
FB
= 100
Ω
, C
FB
= 1nF) placed from the FB pin
to GND can increase stability substantially. The maximum
source current of the FB pin is about 1.2mA. The
phototransistor must be capable of sinking this current to
pull the FB level down at no load. The value of the biasing
resistor, R
BIAS
, is determined as:
Setting the OVP trip point at 22.5V,
K
DET
=
R
DET
1
N
AUX
V
OVP
3 22.5
=
1
= ⋅
1
=
5.75
R
DET
2
N
S
2.5
4 2.5
Then
R
DET
1
=
K
DET
R
R
DET
2
<
134
k
I
DS
V
V
+
V
RO
=
O
.
PFC
.
H
O
.
PFC
.
L
PK
.
K
V
O
.
PFC
.
L
V
O
.
PFC
.
H
+
V
RO
I
DS
=
400 300
+
240
=
1.125
300 400
+
240
PK
.
L
V
O
V
OPD
V
KA
CTR
>
1.2
×
10
3
R
BIAS
(
40
)
Using 113% of 1.125,
V
LIMIT
.
L
=
1.27
=
V
LIMIT
.
H
994
V
O
.
PFC
.
H
994
300
994
V
O
.
PFC
.
L
N
A
+
R
DET
1
N
P
N
A
+
R
DET
1
N
P
where V
OPD
is the drop voltage of photodiode, about 1.2V;
V
KA
is the minimum cathode to anode voltage of shunt
regulator (2.5V); and CTR is the current transfer rate of the
opto-coupler.
3
+
R
DET
1
18637.5
+
R
DET
1
48
=
=
3
24850
+
R
DET
1
994
400
⋅ +
R
DET
1
48
Then,
R
DET1
= 47.5K
Ω
and
R
EDT2
=8.25K
Ω
.
R
DET1
and R
DET2
are selected from the off-the-shelf
components as 150k and 18k , respectively.
Then, the pulse by pulse current limit threshold voltage
is obtained as:
Figure 19. Feedback Circuit
V
O
.
PFC
.
L
V
LIMIT
= −
877
(
=
0.474
V
N
A
0.7
N
P
R
DET
1
+
0.7
)
+
0.882
R
DET
2
(Design Example)
Assuming CTR is 100%;
To set current limit level at low line as 115% of I
DSPK
V
O
V
OPD
V
KA
CTR
>
1.2
×
10
3
R
BIAS
R
BIAS
<
V
O
V
OPD
V
KA
19
1.2
2.5
=
=
12.75
k
1.2
×
10
3
1.2
×
10
3
0.63
=
0.27
1.53
A
×
1.15
330Ω resistor is selected for R
BIAS
.
The voltage divider resistors for V
O
sensing are selected as
66.5kΩ and 10kΩ.
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
www.fairchildsemi.com
12