AN-6920
APPLICATION NOTE
The output is indirectly monitored for over-voltage
protection using the DET pin voltage while the MOSFET is
turned off. The ratio of R
DET1
and R
DET2
should be
determined as:
2
.
5
=
R
DET
2
N
A
N
A
1
V
OVP
=
V
OVP
R
DET
1
+
R
DET
2
N
S
K
DET
+
1
N
S
(
31
)
where the ratio between R
DET1
and R
DET2
is obtained as:
K
DET
=
R
DET
1
N
A
V
OVP
=
⋅
−
1
R
DET
2
N
S
2
.
5
(
32
)
For a quasi-resonant flyback converter, the peak-drain
current with a given output power decreases as input voltage
increases. Thus, constant power limit cannot be achieved by
using pulse-by-pulse current limit with constant threshold.
FAN6920 has high/low line over-power compensation that
reduces the pulse-by-pulse current limit level as input
voltage increases. FAN6920 senses the input voltage using
the current flowing out of the DET pin while the MOSFET
is turned on. The pulse-by-pulse current limit level vs. DET
current is depicted in Figure 18.
The DET pin current for low-line and high-line PFC output
voltages are given as:
V
O
.
PFC
.
L
I
DET
.
L
=
N
A
−
0
.
7
N
P
N
A
−
0
.
7
N
P
Figure 18.
I
DET
-V
LIMIT
Curve
The relationship between I
DET
and V
LIMIT
in the linear region
(I
DET
=100~500 A) can be approximated as:
V
LIMIT
= −
877
⋅
I
DET
+
0.882
(
35
)
R
DET
1
V
O
.
PFC
.
H
+
0
.
7
≅
R
DET
2
0
.
7
≅
R
DET
2
V
O
.
PFC
.
L
N
A
N
P
N
A
N
P
(
33
)
R
DET
1
V
O
.
PFC
.
H
(
34
)
Assuming two-level voltage PFC output: for a given output
power, the ratio between drain-peak currents at low line and
high line is obtained as:
I
DET
.
H
=
R
DET
1
+
R
DET
1
I
DS PK
.
L
V
O
.
PFC
.
H
V
O
.
PFC
.
L
+
V
RO
=
⋅
I
DS PK
.
H
V
O
.
PFC
.
L
V
O
.
PFC
.
H
+
V
RO
(
36
)
For a given output power, the ratio between pulse-by-pulse
current limit levels at low line and high line is obtained as:
V
LIMIT
.
L
≅
V
LIMIT
.
H
−
994
⋅
V
O
.
PFC
.
H
−
994
⋅
V
O
.
PFC
.
L
N
A
+
R
DET
1
N
P
N
A
+
R
DET
1
N
P
(
37
)
To get a constant power limit, R
DET1
should be determined
such that Equations (38) and (39) are equal. However, for
actual design, it is typical to use 108~115% of Equation
(38), considering the pulse-by-pulse turn-off delay and
increased PFC output voltage ripple at low line.
Figure 17. Switching Frequency and Peak-Drain
Current Change as Input Voltage Increases
Once the current-limit threshold voltage is determined with
R
DET1
, the current-sensing resistor value is obtained as:
V
O
.
PFC
.
L
V
LIMIT
= −
877
⋅
(
N
A
−
0.7
N
P
0.7
)
+
0.882
R
DET
2
(
38
)
R
DET
1
+
The current-sensing resistor value can be obtained from:
R
CS
2
=
V
LIMIT
I
DS LIM
(
39
)
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
www.fairchildsemi.com
11
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