AN-6920
APPLICATION NOTE
[STEP-A3] Design V
IN
Sense Circuit
FAN6920 senses the line voltage using the averaging circuit
shown in Figure 12, where the VIN pin is connected to the
AC line through a voltage divider and low-pass filter
capacitor. When V
IN
drops below 1V, the COMP pin is
clamped at 1.6V to limit the energy delivered to output.
V
O.PFC
decreases with the INV pin voltage. When the INV
pin voltage drops below 1V, brownout protection is
triggered, stopping gate drive signals of PFC and DC/DC.
This protection is reset when V
DD
drops below the turn-off
threshold (UVLO threshold). When V
DD
rises to the turn-on
voltage after dropping below the turn-off threshold,
FAN6920 resumes normal operation (if
V
IN
is above 1.2V).
The brownout protection level can be determined as:
V
LINE
.
BO
=
R
VIN
1
+
R
VIN
2
R
VIN
2
2 2
(Design Example)
Choosing the margin factor as 35%,
the sensing resistor is selected as:
R
CS
1
=
0.82
0.82
=
=
0.19
Ω
I
L
.
PK
(1
+
K
MARGIN
) 3.14(1
+
0.35)
[STEP-A6] Design Compensation Network
The feedback loop bandwidth must be lower than 20Hz for
the PFC application. If the bandwidth is higher than 20Hz,
the control loop may try to reduce the 120Hz ripple of the
output voltage and the line current is distorted, decreasing
power factor. A capacitor is connected between COMP and
GND to attenuate the line frequency ripple voltage by 40dB.
If a capacitor is connected between the output of the error
amplifier and the GND, the error amplifier works as an
integrator and the error amplifier compensation capacitor
can be calculated by:
C
COMP
>
100
⋅
g
M
2.5
⋅
2
π
⋅
2
f
LINE
V
O
.
PFC
.
H
(
15
)
π
⋅
(
12
)
The minimum line voltage for PFC startup is given as:
V
LINE
.
STR
=
1.2
⋅
V
LINE
.
BO
(
13
)
To improve the power factor, C
COMP
must be higher than the
calculated value. However, if the value is too high, the
output voltage control loop may become slow.
(Design Example)
C
COMP
>
100
⋅
g
M
2.5
⋅
2
π
⋅
2
f
LINE
V
O
.
PFC
.
H
100
⋅
125
×
10
−
6
2.5
=
⋅
=
103
nF
2
π
⋅
2
⋅
60
400
470nF is selected for better power factor.
Figure 12. V
IN
Sensing Internal Block
Part B. DC/DC Section
(Design Example)
Setting the brownout protection trip point
as 69V
AC
:
R
VIN
1
+
R
VIN
2
2 2
=
V
LINE
.
BO
⋅
=
62
R
VIN
2
π
Determining R
VIN2
as 154k , R
VIN1
is determined as 9.4M .
The line voltage to startup the PFC is obtained as:
V
LINE
.
STR
=
1.2
⋅
V
LINE
.
BO
=
83
V
AC
[STEP-A4] Current Sensing Resistor for PFC
FAN6920 has pulse-by-pulse current limit function. It is
typical to set the pulse-by-current limit level at 20~30%
higher than the maximum inductor current:
[STEP-B1] Determine the Secondary-Side Rectifier
nom
Voltage (V
D
)
Figure 13 shows the typical operation waveforms of a dual-
switch quasi-resonant flyback converter. When the
MOSFET is turned off, the input voltage (PFC output
voltage), together with the output voltage reflected to the
primary (
V
RO
), is imposed on the MOSFET. When the
MOSFET is turned on, the sum of input voltage reflected to
the secondary side and the output voltage is applied across
the secondary-side rectifier. Thus, the maximum nominal
voltage across the MOSFET (
V
dsnom
) and diode are given as:
V
DS
nom
=
V
O
.
PFC
+
n
(
V
O
+
V
F
)
V
O
.
PFC
+
V
RO
=
2
2
(
16
)
where:
R
CS
1
=
0.82
I
L
.
PK
(1
+
K
MARGIN
)
(
14
)
n
=
V
D
7
N
P
V
RO
=
N
S
V
O
+
V
F
=
V
O
+
V
O
.
PFC
n
(
17
)
www.fairchildsemi.com
where K
MARGIN
is the margin factor and 0.82V is the pulse-
by-pulse current limit threshold.
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
nom
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
