AN-6920
APPLICATION NOTE
Printed Circuit Board Layout
Printed circuit board layout and design are very important
for switching power supplies where the voltage and current
change with high dv/dt and di/dt. Good PCB layout
minimizes EMI and prevents the power supply from being
disrupted during surge/ESD tests.
External driver circuit can shorten MOSFET gate
discharge current loop and improve the surge/ESD
capability.
Current loop constructed by the PFC choke, PFC diode,
PFC MOSFET,
C
Bulk
, and
C
2
should be as short as
possible
.
PWM Stage
IC Side
Reference ground of the INV, COMP, CSPFC,
CSPWM, and VDD pins are connected together and
then connected to the IC’s GND directly.
Reference ground of ZCD, VIN, RT, FB, and DET pins
are connected to IC’s GND directly.
Small capacitors around the IC should be connected to
the IC directly.
The trace line of CSPWM, OPFC, and OPWM should
not be paralleled and should be close to each other to
avoid introducing noise.
Connections of IC’s GND,
R
CS.PWM
ground, HV IC’s
GND, and auxiliary winding of PWM XFMR:
Approach
R
CS.PWM
should be connected to
C
Bulk’s
ground directly.
Keep it short and wide.
Current loop constructed by the
C
Bulk
, XFMR, PWM
MOSFET, clamp diode, and
R
CS.PWM
should be as short
as possible.
Ground of photo-coupler should be connected to IC’s
GND.
On the secondary side, current loop constructed by
XFMR, Schottky, and output capacitor should be as
short as possible.
Connections of Y Capacitor:
Approach
Auxiliary winding’s ground
IC’s GND
R
CS.PWM
’s ground (2 1 4)
HV IC’s GND
R
CS.
PWM
’s ground (3 4)
Y CAP’s primary ground
Approach Ground Loop:
C
1
’s ground (10
9)
System Side
PFC Stage
Auxiliary winding of PFC choke is connected to IC’s
GND.
R
CS.PFC
should be connected to
C
2
’s ground singly
(6 & 8).
7&2
3
4
4
5
6
8
8 & 10
1
8
9
4
Figure 22. Layout Considerations
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
www.fairchildsemi.com
16
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