April 1997
NDS351AN
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMCIA
cards, and
other battery powered circuits where fast
switching, and low in-line power loss are needed in a very small
outline surface mount package.
Features
1.2A, 30 V. R
DS(ON)
= 0.25
Ω
@ V
GS
= 4.5 V
R
DS(ON)
= 0.16
Ω
@ V
GS
= 10 V.
Industry standard outline SOT-23 surface mount package
using proprietary SuperSOT
TM
-3 design for superior
thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface mount
_________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
T
J
,T
STG
Parameter
Drain-Source Voltage
T
A
= 25°C unless otherwise noted
NDS351AN
30
20
(Note 1a)
Units
V
V
A
Gate-Source Voltage - Continuous
Maximum Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
± 1.2
± 10
0.5
0.46
-55 to 150
W
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
250
75
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDS351AN Rev. C
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
