HUF75545P3, HUF75545S3, HUF75545S3S
o
Electrical Specifications
PARAMETER
T
= 25 C, Unless Otherwise Specified
C
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
I
= 250µA, V
= 0V (Figure 11)
80
-
-
-
-
-
-
V
DSS
D
GS
GS
GS
I
V
V
V
= 75V, V
= 70V, V
= ±20V
= 0V
1
µA
µA
nA
DSS
DS
DS
GS
o
= 0V, T = 150 C
-
250
±100
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
THERMAL SPECIFICATIONS
I
-
GSS
V
V
= V , I = 250µA (Figure 10)
2
-
-
4
V
GS(TH)
GS
DS
D
r
I
= 75A, V
= 10V (Figure 9)
0.0082 0.010
Ω
DS(ON)
D
GS
o
Thermal Resistance Junction to Case
R
R
TO-220 and TO-263
-
-
-
-
0.55
62
C/W
θJC
o
Thermal Resistance Junction to
Ambient
C/W
θJA
SWITCHING SPECIFICATIONS (V
Turn-On Time
= 10V)
t
GS
V
V
R
= 40V, I = 75A
D
= 10V,
= 2.5Ω
-
-
-
-
-
-
-
14
125
40
90
-
210
ns
ns
ns
ns
ns
ns
ON
DD
GS
Turn-On Delay Time
Rise Time
t
-
d(ON)
GS
t
-
r
Turn-Off Delay Time
Fall Time
t
-
-
d(OFF)
t
f
Turn-Off Time
t
195
OFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
V
V
V
= 0V to 20V
= 0V to 10V
= 0V to 2V
V
= 40V,
-
-
-
-
-
195
105
6.8
15
235
125
8.2
-
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
DD
= 75A,
I
I
D
Gate Charge at 10V
Q
g(10)
g(TH)
= 1.0mA
g(REF)
(Figure 13)
Threshold Gate Charge
Q
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
CAPACITANCE SPECIFICATIONS
Input Capacitance
Q
gs
gd
Q
43
-
C
V
= 25V, V = 0V,
GS
-
-
-
3750
1100
350
-
-
-
pF
pF
pF
ISS
DS
f = 1MHz
(Figure 12)
Output Capacitance
C
OSS
RSS
Reverse Transfer Capacitance
C
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
1.00
100
UNITS
Source to Drain Diode Voltage
V
I
I
I
I
= 75A
= 35A
-
-
-
-
-
-
-
-
V
V
SD
SD
SD
SD
SD
Reverse Recovery Time
t
= 75A, dI /dt = 100A/µs
SD
ns
nC
rr
Reverse Recovered Charge
Q
= 75A, dI /dt = 100A/µs
SD
300
RR
©2002 Fairchild Semiconductor Corporation
HUF75545P3 / HUF75545S3 / HUF75545S3S Rev. C
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
