FM93C66 4096-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
Absolute Maximum Ratings
(Note 1)
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
Lead Temperature
(Soldering, 10 sec.)
ESD rating
-65°C to +150°C
+6.5V to -0.3V
Operating Conditions
Ambient Operating Temperature
FM93C66L/LZ
FM93C66LE/LZE
FM93C66LV/LZV
Power Supply (V
CC
)
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
2.7V to 5.5V
+300°C
2000V
DC and AC Electrical Characteristics
V
CC
= 2.7V to 4.5V unless otherwise specified. Refer to
page 3 for V
CC
= 4.5V to 5.5V.
Symbol
I
CCA
I
CCS
Parameter
Operating Current
Standby Current
L
LZ (2.7V to 4.5V)
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SK Clock Frequency
SK High Time
SK Low Time
Minimum CS Low Time
CS Setup Time
DO Hold Time
DI Setup Time
CS Hold Time
DI Hold Time
Output Delay
CS to Status Valid
CS to DO in Hi-Z
Write Cycle Time
Conditions
CS = V
IH
, SK=250 KHz
CS = V
IL
Min
Max
1
10
1
Units
mA
µA
µA
µA
V
V
KHz
µs
µs
µs
µs
ns
µs
ns
µs
I
IL
I
OL
V
IL
V
IH
V
OL
V
OH
f
SK
t
SKH
t
SKL
t
CS
t
CSS
t
DH
t
DIS
t
CSH
t
DIH
t
PD
t
SV
t
DF
t
WP
V
IN
= 0V to V
CC
(Note 2)
-0.1
0.8V
CC
I
OL
= 10µA
I
OH
= -10µA
(Note 3)
0.9V
CC
0
1
1
(Note 4)
1
0.2
70
0.4
0
0.4
±1
0.15V
CC
V
CC
+1
0.1V
CC
250
2
1
CS = V
IL
0.4
15
µs
µs
µs
ms
Capacitance
T
A
= 25°C, f = 1 MHz or
250 KHz (Note 5)
Symbol
C
OUT
C
IN
Note 1:
Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2:
Typical leakage values are in the 20nA range.
Test
Output Capacitance
Input Capacitance
Typ
Max
5
5
Units
pF
pF
Note 3:
The shortest allowable SK clock period = 1/f
SK
(as shown under the f
SK
parameter). Maximum
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both t
SKH
and t
SKL
limits must be observed. Therefore, it is not
allowable to set 1/f
SK
= t
SKHminimum
+ t
SKLminimum
for shorter SK cycle time operation.
Note 4:
CS (Chip Select) must be brought low (to V
IL
) for an interval of t
CS
in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
Note 5:
This parameter is periodically sampled and not 100% tested.
AC Test Conditions
V
CC
Range
(Extended Voltage Levels)
V
IL
/V
IH
Input Levels
0.3V/1.8V
0.4V/2.4V
V
IL
/V
IH
Timing Level
1.0V
1.0V/2.0V
V
OL
/V
OH
Timing Level
0.8V/1.5V
0.4V/2.4V
I
OL
/I
OH
±10µA
2.1mA/-0.4mA
2.7V
≤
V
CC
≤
5.5V
(TTL Levels)
4.5V
≤
V
CC
≤
5.5V
Output Load: 1 TTL Gate (C
L
= 100 pF)
4
FM93C66 Rev. C.1
www.fairchildsemi.com
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
