FM93C66 4096-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
Timing Diagrams
(Continued)
ERASE CYCLE (ERASE)
t
CS
CS
SK
DI
1
Star t
Bit
1
1
A7
A6
Address
Bits(8)
A1
A0
t
WP
Ready
Busy
Opcode
Bits(2)
DO
93C66:
Address bits pattern -> User defined
High - Z
ERASE ALL CYCLE (ERAL)
t
CS
CS
SK
DI
1
Start
Bit
0
0
A7
A6
Address
Bits(8)
A1
A0
t
WP
Ready
Busy
Opcode
Bits(2)
DO
High - Z
93C66:
Address bits pattern -> 1-0-x-x-x-x-x-x
; (x -> Don’t Care, can be 0 or 1)
CLEARING READY STATUS
CS
SK
DI
Star t
Bit
DO
High - Z
Busy
Ready
High - Z
Note: This Star t bit can also be par t of a next instr uction. Hence the cycle
can be continued (instead of getting ter minated, as shown) as if a new
instr uction is being issued.
10
FM93C66 Rev. C.1
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